Non-combinational area is generally just the size of the sequential elements in your design (flip flops, latches, rams, etc). Did you include any of these when you created the clocks?
Rather than addressing the many problems in your source code, let me just show how I'd implement the module you describe.
First, I wouldn't use a sub-module to build the adder; synthesis tools are perfectly able to create adders from behavioral code. Secondly, an elaborate state machine isn't required; the module can simply produce a final result four clocks after each activation of the start
signal. I've added a done
signal to the module interface to make this explicit.
module seq_mult_4bit (
output [7:0] product,
output done,
input [3:0] a,
input [3:0] b,
input clock,
input start
);
reg [7:0] product;
reg [3:0] multiplicand;
reg [3:0] delay;
wire [4:0] sum = {1'b0, product[7:4]} + {1'b0, multiplicand};
assign done = delay[0];
always @(posedge clock) begin
if (start) begin
delay = 4'b1000;
multiplicand = a;
if (b[0]) begin
product <= {1'b0, a, b[3:1]};
end else begin
product <= {1'b0, 4'b0, b[3:1]};
end
end else begin
delay = {1'b0, delay[3:1]};
if (product[0]) begin
product <= {sum, product[3:1]};
end else begin
product <= {1'b0, product[7:1]};
end
end
end
endmodule
If you really want to use an external module for the adder (which is really the point of your question), simply substitute the wire declaration above with the following block of code:
wire [4:0] sum;
rca_4bit adder (
.sum (sum[3:0]),
.c_out (sum[4]),
.a (multiplicand),
.b (product[7:4]),
.c_in (0)
);
Let me know if you have any specific questions about how this implementation works.
Best Answer
You can't instantiate modules in always block. Do it before and assign a clock to that module.