Electronic – What does non-combinational area represent in synopsys design compiler

digital-logicsynthesisverilog

I have designed a ripple adder using full adders. In order to find delay incurred to perform this addition I included a clock in each full adder module. In my main code I instantiated these modules to construct the ripple adder. When I synthesised the ripple adder code and found the area the result was something like :

combinational area=54
non-combinational area=204;

I want to know if this non-combinational area is due to overhead of including clock in each module. Is there any way to reduce this non-combinational area.

Best Answer

Non-combinational area is generally just the size of the sequential elements in your design (flip flops, latches, rams, etc). Did you include any of these when you created the clocks?

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