I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. The rapid-recompile button is always grayed out, I don't even know what it does, I've never had the option. A lot of times, I'm not changing my design just SignalTap, but Quartus wants to recompile everything which seems like a waste of time. Is there a way speed up the compile time (or changes to only apply to SignalTap)? Using Quartus 15.1
Electronic – Improve Quartus partial compile or recompile time
fpgaintel-fpgaquartus
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Best Answer
I've listed some useful flags to make Quartus synthesize faster if you don't care about fully optimizing your results:
Note that this has the caveat below, although I tend to see overall faster runs.
And instead of
Use:
In a meeting with Intel/Altera engineers, using
-implement
this was ball-parked to be about 20% faster than-compile
, and came recommended when iterating on timing-closure results.If anyone has other recommended, please edit this comment so we can develop a list.