Electronic – In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size

If you have a device which puts out 16 bits, and you want to use all of its storage, then in theory what you can is:

• in the reading direction, take the 16 bit output obtained from your address lines A1..AN and pass it through a bank of 2x1 multiplexers, to go from 16 to 8 lines. Your A0 line to drive these multiplexers, so that in effect your A0 line selects which of the two 8 bit halves of the 16 bits are passed to your data bus.

• in the writing direction, you need some buffers which drive each of your 8 lines to one of two possible data pins on the ROM based on address A0.

These two directions can be combined into one using bidirectional multiplexers. For instance, the ON Semiconductor 74FST3257 mux/demux/bus switch provides four 2x1 bidirectional muxes. With a pair of these, you could route 8 points on one side into a choice of two different sets of 8 points on the opposite side, based on the A0 line.

This is complicated enough that it should send you looking for an 8 bit memory part in the first place.

Every row/column intersection on a DDR3 chip addresses 1 byte wide, not 1-bit. So 1024 columns times 8bytes is 8KB / page (row). From micron's data sheet, I observe that 8 bytes of data are fetched at a time into a FIFO using the upper-address lines of the column address. Then the lower 3 lines of the column address are used to select the particular byte from the FIFO. This is for x8 design. For x16, it would fetch 16 bytes (128 bits) from the row and place it in the FIFO, and then use the lower 3 bits to fetch one of the 8 16-byte data.