Electronic – In disassembly, I see instruction LI, but I can’t find such instruction in MIPS instruction set

mipspic

I have little test project for PIC32MX CPU, here's a part of disassembly:

(I know this code is not atomic, I'm just testing things. Actually, I'm pretty newbie in MIPS)

 72:                        LATEbits.LATE0 ^= 0x1;  //-- toggle LATE0
9D0015BE      B309   LW V1, 36(PC)
9D0015C0      9B80   LW A0, 0(V1)
9D0015C2      6A01   LI V0, 1       <--- what is this?
9D0015C4      6D01   LI A1, 1       <--- and this one
9D0015C6      EC4C   AND A0, V0
9D0015C8      EC11   ZEB A0
9D0015CA      ECAE   XOR A0, A1
9D0015CC      EC4C   AND A0, V0
9D0015CE      9B40   LW V0, 0(V1)
9D0015D0      4DFD   ADDIU A1, -3
9D0015D2      EAAC   AND V0, A1
9D0015D4      EA8D   OR V0, A0
9D0015D6      17EF   B 0x9D0015B6
9D0015D8      6100   BTNEZ 0x9D0015DA
9D0015DC      6120   BTNEZ 0x9D00161E
9D0015E0      6120   BTNEZ 0x9D001622

Is command LI an alias for something? I have checked MIPS Architecture For Programmers Volume I-A and II-A, but don't see any occurence of LI.

More, I have this assembly code (it is from TNKernel RTOS, I'm not author of this code):

tn_enter_critical:

        la      $t0,    tn_sys_context
        lw      $t0,    0($t0)
        bne     $t0,    $zero,      1f          /* return if non-task context */
        nop

 ....................

There is instruction la in this code, and in disasm this instruction is shown as LUI:

                                                  119:   tn_enter_critical:
                                                  120:           
9D000020  3C08A000   LUI T0, -24576               121:           la      $t0,    tn_sys_context
9D000028  8D080000   LW T0, 0(T0)                 122:           lw      $t0,    0($t0)
9D00002C  15000006   BNE T0, ZERO, 0x9D000048     123:           bne     $t0,    $zero,      1f          /* return if non-task context */
9D000030  00000000   NOP                          124:           nop
                                                  125:       
 ....................

Now, reversed situation: I see instruction LUI in the docs, but can't find LA. It makes me believe that there really should be aliases, but I can't find them too.

Please explain it to me.

Best Answer

Oh, I really missed that I use -mips16 compiler option. So, LI instruction is definitely from there (here's MIPS16e docs)

As to that la, it seems to be Assembler pseudo-instruction, which is specified in MIPS32 Instruction Set Quick Reference.

Thanks to guys from Microchip forum for help.

Related Solutions

Electronic – Range of MIPS j instruction

Addressing in most CPU cores I know works on a per-byte basis. You don't address individual bits.

The MIPS requires it's instructions to be 4-byte (word) aligned - i.e. the two LSBs are always zero. That way, they're not encoded in the instructions.

@sherrelbc's answer explains it quite thoroughly, although I like the semantics of "word-aligned" more, than "word-addressed".

The link @valcroft gave also has the answer mid-page:

Pseudo-Direct Addressing

Direct addressing means specifying a complete 32 bit address in the instruction itself. However, since MIPS instructions are 32 bits, we can't do that. In theory, you only need 30 bits to specify the address of an instruction in memory. However, MIPS uses 6 bits for the opcode, so there's still not enough bits to do true direct addressing. Instead, we can do pseudo-direct addressing. This occurs in j instructions.

| Opcode  |              Target              |
|---------|----------------------------------|
|  B31-26 |               B25-0              |
| oooo oo | tt tttt tttt tttt tttt tttt tttt |

26 bits are used for the target. This is how the address for pseudo-direct addressing is computed.

PC <- PC31-28::IR25-0::00

Take the top 4 bits of the PC, concatenate that with the 26 bits that make up the target, and concatenate that with 00. This produces a 32 bit address. This is the new address of the PC.

So, 26 bits left shifted by two gives a relative address boundary of \$2^{28}.\$

\$2^{28} bytes\$ is \$256 MiB\$, or \$256*1024^2\$.

Assembly language that corresponds to machine instruction in MIPS

I believe it is a bitwise and immediate AND.

You had the first two steps right:

OX3062FF80
0011 0000 0110 0010 1111 1111 1000 0000

But not the rest.

First separate out the opcode, starting from the left. All opcodes are 6 bits.

So the opcode in binary, from the left, is:

which is 0xC. This is an andi instruction.

Then you need to separate out the fields according to the MIPS I instruction format;

001100  00011  00010  1111 1111 1000 0000 

opcode    rs    rt        immediate

Opcode:     0xC
rs:         0x03
rt:         0x02
Immediate:  0xFF80

I wrote some code and checked that an adi instruction has the above format in a disassembly listing.

To convert this into a assembly instruction:

The assembly language format of an andi is:

andi,rs,rt,IMM

Looking up the MIPS registers for the rs and rt fields:

rs = 0x03 => $v1
rt = 0x02 => $v0

so the corresponding assembly instruction is:

andi $v1,$v0,0xFF80

Best Answer

Related Solutions

Electronic – Range of MIPS j instruction

Pseudo-Direct Addressing

Assembly language that corresponds to machine instruction in MIPS

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