computer-architecturedigital-logicmips
I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies won't cause any hazards.
So i was wondering if there exists processors with hazards because of this WAW and WAR dependency?
If there are, please can you name some of them. Thank you! (I searched google but found nothing useful)
The DRAM works much like a 1T or 3T analog Sample and Hold, except the voltage decays and must be refreshed which consumes less space for high density DRAM but consumes more power due to the charge refresh rates putting in charge current. Newer DRAM's use 4 or 8 level voltages to store 2 or 3 binary bits for the highest density DRAMs. This requires a simple flash ADC/DAC to convert these levels in bits.
SRAM's require at least 4T or 6T NFETs and use positive feedback of the cross-coupled NFETs as a flip flop with a weak drain pullup. Since one side is active LOW, it ensures under "most" conditions that this logic level remains static as long as power is applied ( Volatile)
The binary state is stored as complementary logic levels and read as a differential voltage from 2 other NFET gates when addressed going to a differential comparator or "sense amplifier"
SRAMs can be faster but more expensive since they require more transistors per cell.
S in SRAM means it is still Static.
If the transaction is indicated as "non-modifiable," and both the Read and Write commands use the same ARID/AWID, the order must be preserved. This doesn't cover the case of simultaneous Read and Write commands, which is certainly possible for AXI.
Here's some additional info I found in section A4.3.2 of the AXI Spec (ARM document IHI 0022F.b). My answer is an interpretation of this excerpt:
Ordering between the independent read and write channels can only be guaranteed if a transaction in one direction is issued only after any earlier transaction in the other direction has received a response. If a transaction in one direction is issued before receiving the response to any earlier transaction in the other direction, then no ordering exists between the transactions.
If both transactions arrive at the AXI slave simultaneously, the behavior depends on the slave. For a dual-port RAM, you could conceivably read while writing to the same address. The Read result would then depend on the dual-port RAM controller. For something like DDR3 which can't have simultaneous R/W, the ordering behavior depends on the R/W priority in the controller, again.
Later in section A6.1, this is confirmed even more explicitly:
Read and write address channels are independent and in this specification, are defined to be in different directions. If an ordering relationship is required between two transactions with the same ID that are in different directions, then a master must wait to receive a response to the first transaction before issuing the second transaction.
Best Answer
All pipelined processors are susceptible to this. There's a particularly good technote on resolving this on the SPARC due to the pipeline and local register windowing with functions.
In the code above, the Read-After-Write hazard exists as 2 reads $1 before the writeback. If you have pipeline of any depth.
Write-After-Read and Write-After-Write dependencies do not cause pipeline hazards.