Electronic – Interfacing open-collector optoisolator to 3.3V microcontroller

That's right, open collector is BJT, open drain (C)MOS. In logic circuits where currents are low the saturation voltage of the BJT may be a bit higher than the voltage drop due to \$R_{DS(ON)}\$ for the FET, but it still will be much lower than the maximum voltage for a logic low.

Exception: you can't use a TTL open collector output as a level shifter to interface with very low voltage CMOS. This inverter can operate on a Vcc as low as 0.8 V, and the datasheet gives a maximum low level of 0.25 Vcc, that's 0.2 V. An open collector will have a voltage drop higher than that. (This device even specifies a maximum low level input voltage of 0 V, which is simply impossible.)

note
Apart from wired-ORing (think I2C) open drain/collector is often used to control something operating at a different voltage than the logic, often a higher voltage. With some low-voltage logic families this no longer possible, since the FETs will not tolerate the high voltage and for that reason some families will have clamping diodes built-in to protect the output FETs.

A couple of thoughts:

1. To make an opto's output transistor switch on hard, quickly, you need to put a lot of current into the LED briefly, but I don't know that you'd have to keep it on that hard. I would think that driving the LED briefly with a higher current and then using a lower current to hold it might be helpful; if the time between cutting back on the holding current and switching it off altogether was sufficient, that reduced holding current could help the transistor switch off more quickly.
2. It might be helpful to add some circuitry on the output side of your opto. You may have to switch 15mA, but that doesn't mean the opto has to do so. If you will only have to start asserting the output when it's high (meaning you won't have to do things like stretch pulses which originate with other devices) and won't have to hold it too long, you could perhaps use an NFET, a diode, a small cap, and two optos. One opto would connect the gate of the NFET to the drain via diode. The other would connect it to the source. The drain would have a small cap to the source to maintain the gate voltage while the NFET is on. To start asserting the output, one would pulse the opto connecting the gate to the drain. To stop asserting it, one would pulse the opto connecting the gate to the source. When the device is idle, one should drive the latter opto just enough to overcome any possible leakage through the former. There are many possible variations on this circuit; having a "supply" capacitor may be better than having a capacitor on the gate, but putting the capacitor on the gate would probably yield more consistent behavior (since the capacitor would always start discharged when one started to assert the output, and since releasing the output would not require charging the cap).

Depending upon how much voltage drop you can tolerate, other approaches may be workable as well. For example, you might be able to use an opto together with a BJT to form a Darlington arrangement, but use a second opto to accelerate the turn-off behavior. Such an approach would have a much higher voltage drop than the MOSFET-based approach, but would eliminate any need for a capacitor.