The first comprehensive logic series was the TTL series 74xx. This used BJTs (Bipolar Junction Transistors). Later there came variants like the often used 74LSxx, where the "LS" stands for Low-power Schottky TTL. As the name implies these used less power than the rather power-hungry TTL, and were faster too. At the same time the CMOS 4000 series was developed. The "C" in CMOS stands for Complementary, meaning it's a combination of N-channel and P-channel MOSFETs. Their construction is simpler than TTL and they use far less power. Later standard CMOS developed into HCMOS, "H" for High-speed. Most 74LSxx types have been released as HCMOS in the 74HCxx series, or the 74HCTxx series, which is TTL compatible. Later more variants were developed, like Advanced CMOS (74ACxx).
Microcontrollers are built in HCMOS technology, so they use MOSFETs. AFAIK JFETs aren't used for logic ICs. The transistor you show in the picture is a BJT, which you can tell from the pin designation:
E = Emitter
B = Base
C = Collector
For a MOSFET the pins would be
S = Source
G = Gate
D = Drain
respectively.
Many ICs in the 74HCxx series were originally released in 14 or 16 pin DIL packages, which meant that they would fit four 2-input gates. With miniaturization (SMT) came the demand for smaller packages, even if they contained less gates. Several manufacturers offer single-gate and dual-gate versions of logic gates. For example, NXP has a 74LVC1G00 (single 2-input NAND) and a 74LVC2G00 (dual 2-input NAND) version of the classical 74HC00. 74LVCxx is yet another HCMOS technology. This page lists all NXP logic families.
"Lets consider a SR Latch built with NOR gates. The invalid inputs are S=1, R=1. With enabled latch [gated latch], the invalid inputs are same, S=1, R=1."
That is true only when the gating does not invert the signal (for instance two AND gates).
"Now, lets consider, NAND gates, in SR Latch, the invalid inputs are S=0, R=0. But in enabled SR latch, the invalid inputs are S=1, R=1"
Correct, because the gating inverts the S and R signals.
"So, can I say, invalid inputs with SR Latch with NAND are: S=1, R=1"
Correct
"If enabled, then S=0, R=0"
That is half-true. You should be able to formulate the fully-true answer by yourself.
Best Answer
Well, in CMOS usually all functions are inverting. The most simple logic function you can implement is a NAND or a NOR (besides the inverter).
OR an AND Gates in cmos logic are basically NOR and NAND with an inverter behind.
Use De Morgan's law (https://en.wikipedia.org/wiki/De_Morgan%27s_laws) and the rules of boolean algebra to convert your formula:
$$Y=(¬A∗¬B)+¬C+¬D$$
$$Y=¬(A+B)+¬(C*D)$$
Now it depends on your hardware constraints, if you want to have a solution with minimal gates or with more gates but a smaller "fan in" (more input gates make your circuit slower).
A solution with minimal fan in would be
simulate this circuit – Schematic created using CircuitLab
This can be translated to cmos 1:1 by using the standard layout for cmos gates.
Now if you want to have a single gate, it gets trickier. Convert the formula one step further to get an inversion as the outermost operator: $$Y=¬((A+B)*(C*D))$$
You can see that the basic structure is a NAND gate. Now you have to design the pull up network and the pull down network.
For the pull down network, an AND in the logical formula means to connect the transistors in series and for an OR you have to connect them in parallel. For the pull up network it is vice versa.
The pull down network would look like this:
simulate this circuit
And complementary the pull up network:
simulate this circuit
Now combine them and you are done. If you have inverted inputs in the last formula, you have to invert the inputs with an separate inverter before connecting them to the gate.