Electronic – IO clock pin far from design, reduce propagation delay

clockiotiming-analysis

My design is deployed around a particular tile in the FPGA, mainly because of a gigabit transceiver that is located there.

However one of the clocks needed for the gigabit transceiver has to come from a pin that is on the far end of the die.The propagation delay of that clock causes timing errors.

What would be a way to reduce the propagation delay of a clock in such an arrangement?

Best Answer

Two key concepts:

FPGAs in general (and Xilinx FPGAs in particular) have clock distribution networks that are designed to deliver clocks with low skew across the entire chip.
A PLL (or DCM) can be used as a zero-delay clock buffer.

Combining these concepts gets your clock across the chip with essentially zero delay.

schematic

^{simulate this circuit – Schematic created using CircuitLab}

The PLL adds enough delay so that the total delay through it and the clock distribution network is exactly one clock period. Since that means there is essentially zero delay between the PLL inputs, and there is zero delay among the loads of the clock tree, the transceiver gets a clock that has essentially zero delay from the input pad on the other side of the chip.

Related Solutions

Electronic – Does it always make sense to constrain an I/O port

Well, it does make sense to apply meaningful constraints if you actually care about timing and it does matter. How to constrain it heavily depends on your design. Thankfully, Altera has tons of examples for different cases.

But if you don't care at all then the best way to go is to mark that path as a false path so that Time Quest is happy and synthesizer does not hang for hours trying to route your design in order to meet timing requirements that you don't really have. That you can do with set_false_path command. For example:

set_false_path -from * -to [get_ports { output_port }]

(where output_port is a module's top level port assigned to a pin)

If Time Quest gives you a diagnostics that not every output port has a delay, you may want to add some dummy delay as well, like this:

set_output_delay -clock [get_clocks src_clk] 2 [get_ports { output_port }]

For a more practical example, you can check out this SDC file for this top-level module, the path to led_n is market as false path there since I pretty much don't care about timing from my logic to the LEDs.

Hope it helps.

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

I'd say that the rule of thumb is: set either input port of the top module, or Q pin of an internal flip-flop as the source of generated clock.

Example Verilog code:

module top (

input clk,
input rst,

...

);

...

always @(posedge clk or negedge rst)
begin
if (rst == 1'b0) 
    div_2_clk = 1'b0;
else
    div_2_clk = ~div_2_clk;           
end

...

endmodule

Example SDC code:

create_clock -name clk -period 5 [get_port clk]
...
create_generated_clock -name slow_clk -source [get_port clk] -divide_by 2 [get_pins div_2_clk_reg/Q]

I did no test the above syntax's. Also note the extension _reg added to the RTL name of the signal - this is the extension added by synthesis tool when it detects that the signal must be represented by a flip-flop. This extension may vary between tools (I don't know for sure).

If you use any RTL wrapper around flip-flops - set the source of the generated clocks to be the internal Q pin of the flip-flop, not the output pin of the wrapper.

If you follow these simple rules you need not worry about any buffers added by the synthesis or P&R tools.

Best Answer

Related Solutions

Electronic – Does it always make sense to constrain an I/O port

Electronic – ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock

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