- The loop bandwidth is controlled by the gain of the loop.
This gain includes the phase detector gain, any dividers in the loop, and the VCO tuning constant. If we break the loop at the VCO tuning input, we are controlling the frequency, but measuring the phase. This gives us a pure integrator. The loop has an irreducible 90 degrees phase shift to go with its falling frequency response.
- The loop bandwidth is just one of many factors affecting the output phase noise and jitter.
The reference input frequency has phase noise and jitter. The VCO in the PLL has phase noise and jitter. The output signal comprises mostly the reference jitter below the loop bandwidth, and mostly the VCO jitter above the loop bandwidth.
If the output has too much of the VCO noise in it below the loop bandwidth, then we can increase its rejection by adding integrators below the loop bandwidth, broken back at the loop bandwidth for stability.
If the output has too much of the reference noise in it above the loop bandwidth, we can improve the rejection by adding low pass filters above the loop bandwidth, far enough above for minimal additional phase shift at the loop bandwidth.
- A wider loop bandwidth generally means faster lock time. Badly chosen loop filter frequencies can extend the lock time by making it slightly unstable.
Some PLL's actually adjust the loop bandwidth on the fly. When the PLL has not locked, the bandwidth is high and lock time is improved. But after locking, the bandwidth is reduced to reduce the reference jitter and noise.
Have you looked at the datasheet of the 4046 PLL ? The 4046 contains both types of PD.
The type-1 PD implemented as an XOR outputs 0 when both it's input signals are equal and outputs a 1 when they are not. It cannot distinguish between both signals so it cannot detect if Fvco is too high or too low. It can only detect that it is "not the same" as Fin.
At phase = π the signal inverts so at phase = π - delta the PD's output signal is the same as what it is at phase = π + delta. This explains the positive slope changing to a negative slope at phase = π. The input signal inverts but the XOR treats it the same way, it cannot do any better !
"Why would a PLL with this type of PD not lock if the phase difference input to the PD is greater than 2π?"
Your assumption is wrong, it does lock.
Let me explain:
I give you two signals and a 4 channel oscilloscope.
At t = 0 I provide you with 3 signals:
signal A is a 1 kHz sinewave starting at phase = 0
signal B is a 1 kHz sinewave starting at phase = π
signal C is a 1 kHz sinewave starting at phase = 10 π
Now tell me which signal is which !
Think about it before reading any further !
The answer is that you can only tell me which is signal B.
You cannot distinguish signals A and C because a sinewave repeats
itself every 2π of the phase.
Like you, a type-2 PD also cannot distinguish signals which are shifted by 2π
so it will treat a phase of delta the same as a phase of delta + 2π
or delta + 4π. That is why the graph only shows 0 to 2π, the graph repeats itself every 2π just like a sinewave.
It can however distinguish a phase of π - delta from a phase of π + delta !
That is it's advantage over a type-1 PD.
For a type-2 PD it is not the absolute phase that is locked, it is the modulo(2π) of that phase and that is OK as the signal repeats.
Best Answer
An "unlocked" PLL could be open or closed loop.
Consider if the capture range does not exceed the initial mixer error frequency then the feedback is too small to correct the VCO and lock it even though, the loop may be "closed"
Capture range is usually much less than the holding or tracking Locked range for a type I phase detector mixer.
This capture/ Locked range ratio depends on the loop phase margin, which depends on the loop filter phase lead /lag compensation which is a fancy description for a filter that looks like < R1+R2C1> in the feedback path .