I suspect you are a C language programmer.
IC datasheets are generally written to a target audience of assembly language programmers, who need to be aware of many quirky little details.
Often C language programmers are happy to let pre-written library functions take care of most of those details, rather than re-writing everything from scratch.
Alas, the people who write those libraries often let some of the quirky little details show through.
There are two popular ways to store data to flash memory: let some library functions handle the quirky bits for you, or write your own functions to handle the quirky bits.
Using the library functions
Using "Data EEPROM Emulation" library that you linked.
There are several ways of using its functions to read and write your data, to store your 1024 bytes of data, such as "8 virtual EEPROM banks with 128 bytes in each bank."
Check out the "PIC24/dsPIC33F/dsPIC33E Emulation Checklist" in AN1095.
In principle, it explains how to use that library to store stuff in flash in relatively clear English.
You edit the "DEE Emulation 16-bit.h" file, add that file and a few other library files to your project.
When your program runs, it calls the DataEEInit() function during boot-up initialization.
Later your program calls DataEERead() to read the latest version of your data values from flash, or calls DataEEWrite() to write new version of your data values to flash, or both.
Since it does wear-leveling, the latest version of the data is stored at different addresses at different times -- it allocates the memory for you, and keeps track of the address of the latest version of your data. So there's no point in creating your own variable "nvram" at some fixed address to refer to that data, since even if that happens to point to the correct address at one time, sooner or later that data will move to some other address, and that variable will be left pointing to old stale data.
writing your own library functions
The __builtin_tblpage() gives the "high part" of an address when divided up in the right way for the TBLRD and TBLWT instructions to read and write flash.
The __builtin_psvpage() gives the "high part" of an address when divided up in the right way for PSV to read flash. (My understanding is that the only way for a program running on that chip to write values to its program flash is with the TBLWT instruction; those values can later be read with either TBLRD or PSV).
The slight difference between these two ways of dividing an address into a "high part" and a "low part" is implied in the "dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04
Data Sheet" that you linked to, in 4 pages of the datasheet starting with "4.6 Interfacing Program and Data Memory Spaces" and "TABLE 4-39: PROGRAM SPACE ADDRESS CONSTRUCTION".
1) How do you reliably allocate the memory [at some specific address] ?
Alas, this is different for every programming language, and is different even between different C compilers.
The "MPLAB C30 C Compiler User's Guide" and its documentation updates
would be a good place to look for this information.
I think you will also be interested in the documentation for
void _erase_flash(_prog_addressT dst)void _write_flash16(_prog_addressT dst, int *src)_PROGRAM_END
The behavior you observe is due to SPIxCON.MSSEN bit being set ( it is cleared by default so apparently it was you who set it blindly before understanding how it works - sorry, couldn't resist ). In this mode SS stays asserted as long as there is data to be transmitted, and it will stay low if you happen to write to the buffer during transmission. This as well as other useful and fascinating things can be learned by studying Section 23 of PIC32 Family Reference Manual, a link to which is conveniently provided on any PIC32 micro product page at Microchip web site.
You don't have to do this though. Just leave this bit in its default state and drive SS manually.
Best Answer
The amount of silicon required to address less than 2n but more than 2n-1 pages/rows/columns/cells/etc is the same as the amount of silicon to address exactly 2n. So the silicon usage efficiency is best at 2n.
Further, if you intend to put several of them together in a parallel access scheme, you will end up with gaps if each chip doesn't address 2n.
There's little advantage to supporting sizes between 2n and 2n-1.
If you need to create a device with memory in the range 2n and 2n-1 then you will generally find that buying the 2n part is more cost effective than buying the 2n-1 part and a smaller part. Manufacturers have the same issue when producing silicon dies. Yes, they could make one, but it wouldn't increase their bottom line.