Electronic – Is it possible for a VHDL component to have multiple architectures

1. To use multiple architectures in a single entity, the structure you're looking for (I believe) is configurations. I could never make heads or tails of configurations, and the usage is arcane as best I can tell. Best of luck if you try it.
2. The half-assed way of doing it would be to use an if generate statement with a generic parameter selecting which instantiation to use. This requires having seperate entities for each architecture, and third entity to act as a wrapper around the generate statement.
3. The really lazy way would be to just directly instantiate your HalfAdder and RippleCarryAdder as seperate modules, and ignore the headache altogether.

I've never attempted any of this, and I haven't used ISE in years. I don't know if it does support funky configurations, and it honestly wouldn't surprise me if didn't. Like everyone else was saying, I'd suggest upgrading to Vivado

In VHDL and in everything, there is never too many comments. Comments save a lot of time when somebdy else needs to continue your work, or interface it, or just understand it. Thus, each entity, signal and process needs to be explained.

There are also others convention, such as naming and make your code as clear as possible by indenting, align the entity port etc.

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You need to explain the entire module (entity + architecture) : what is it for, how does it work, how does it interface with other modules. Then you can specify the program developement unit, file, device, and autor of the module. You can inlcude an history, and what Tools do you use for simulation, synthesis, routing, how long should you simulate.

For the entity you explain what is it for and how does it work.