Is it possible for (W/L) of 0.18nm PMOS to become 989100 ? If not,i wonder what the range is for (W/L) of TSMC 0.18nm PMOS and NMOS.Thanks a lot.
Electronic – Is it possible for (W/L) of 0.18nm PMOS to become 989100
mosfetnmospmos
Related Solutions
Microchip designer here...
I've never heard of a "fat" MOS transistor, but there is such a thing as a "thick oxide" MOSFET transistor, sometimes referred to as just "thick" transistors.
Typically, a MOSFET transistor is designed such that the electrical performance is good for a particular voltage range. For example, 0.7 to 1 volts. That means that it switches pretty fast, and its leakage current is acceptable.
But sometimes you want a transistor to be a little speedier switching. So you'll make the gate oxide a little thinner than typical. This is known as a "thin oxide" MOSFET transistor.
A thin oxide transistor's Vt (threshold voltage) is lower than the typical gate oxide transistor's Vt, so it will switch faster and stronger. But it also means there's more leakage, which means there's wasted power and a build-up of heat. If it wasn't for that, we'd just design all the transistors with thin-oxide.
As for thick-oxide transistors, that's the opposite of a thin-oxide transistor. The Vt (threshold voltage) goes up. Switching speed goes down. Leakage current and heat also goes down. The reason thick-oxide transistors are used is mostly because the voltage applied to these devices is much higher than typical transistors. With higher voltages, you need more of an insulator (oxide layer) at the gate. Otherwise it will stress the gate terminal too much and cause catastrophic damage to it.
Why do you need to handle different voltages on the same chip? The answer is that in the "core" of your design, where you're actually handling all of the logic functionality, you will use whatever voltage is optimal for that particular semiconductor process technology and your design goals. But when you have to interface your chip with the outside world, you'll have to use whatever voltage is best to do that. Typically, that voltage is much higher than the core voltage. So the core might be at 1V, but the I/O interface might be at 1.7 to 3V. And for those, you'll need to use thick-oxide devices.
If you're referring to the width of the transistor when you say "fat" MOSFETs (which I've never heard before), then yes it's just a wider transistor than normal. The thing is, there really aren't "wide" transistors and "thin" transistors. In almost every semiconductor process technology I've seen, the width of the MOSFET transistors varies along a range. So for example, from 10 nanometers to 10 micrometers in the same technology. That's a pretty big range. And so in any given microchip design, you'll see transistors with all different widths. It just depends on what kind of functions you're trying to perform on the chip. Rarely are you going to see transistors that are super wide (like 10 microns wide when most transistors are under 0.1 microns). But I suppose if you do see that, then those you could conceivably call "fat" transistors.
There are extremely few situations where a depletion mode MOSFET is necessary or preferred. It is extremely unlikely that you happen to have an application where you need to use such a device.
There is no reason to think that a depletion mode device will be as fast reacting as alternative more modern components. If you want it to act as a switch then you will need to hold it off until it needs to be on, and there is no reason that off to on speed of depletion mode device is especially fast compared to alternatives
Achieving fast reacting" circuits is 'just a matter of design'.
If you describe your requirement (rather than an assumed solution) in detail we will be able to assist you with a good solution using readily available components.
What order of switching speed do you require? Please tell us as much as possible about your application.
Best Answer
Theoretically you can make any W/L you want. But as the ratio gets higher you might want to look for alternative plans, such as transistors in parallel.
I'm assuming you mean a 0.18 um process since I don't believe TSMC, or anyone, has a 0.18 nm process. If so a W/L of 989100 and L = 0.18 um would give you a width of 17.8 cm. This is a bit absurd and would make for a very large, or strangely shaped, die. Both of which I'm sure you would want to avoid.
TSMC published rules for their different processes. It is likely that the maximum dimensions are provided there. If not, then I would assume they define no limits and if you are okay with the die size, then you can go for it.
When designing a circuit with FETs you can generally make any W/L you want, but as I mentioned earlier, this might make the dimensions of your FETs undesirable. You can instead replace a FET of width
W
with the parallel combination ofn
FETs of widthW/n
as shown:In this image, all three combinations of FETs "should" work the same. There will be some slight differences between these designs that I'm ignoring, but they should be relatively minor.