Electronic – Is it possible to have a register with multiple drivers

hdlregisterrtlverilog

This is just a theoretical question I have. Imagine we have a register (a reg signal in Verilog for example) and two possible inputs that have to write to that register. I am assuming all signals are synchronous to the same clock. Normally in these cases I guess that you need a multiplexer to decide which signal actually go to the input of the register. But, it is possible to connect both signals to the input without any multiplexer? I am assuming that at all times only one source wants to write to the register. I have this question because I'm wondering if it is possible to avoid using the multiplexer and thus reducing resource usage in the final circuit.

Thank you in advance

Best Answer

It's possible to do this in certain technologies, like bipolar open collector and custom cmos. But you won't see this available for most synthesis tools to implement directly in and FPGA or ASIC.

With open collector, you declare a net as tri1 or a wire with an attached pullup. Or you can use the wand net directly. Each open collector driver can pull the net to 0, but all have to be off to have the net be 1. I2C protocol uses this technology for intra-board communication. There are other technologies that give you a wire-ed NOR.

Related Solutions

Electronic – Is making a D flip flop with asynchronous level triggered reset possible

Here's Xilinx's example of a "Flip-Flop with Negative Edge Clock and Asynchronous Reset":

always @(negedge C or posedge CLR)
    begin
        if (CLR)
            Q <= 1’b0;
        else
            Q <= D;
    end

(Source: Synthesis and Simulation Design Guide, UG626, Oct 19, 2011)

Notice that this is basically the same as your second example (except using the opposite clock edge). And in fact this is a level-sensitive clear, not an edge-sensitive clear, because if clear is held high, the output will continue to be held low, even if new clock edges arrive and/or the D input changes.

Electronic – Verilog memory designs with multiple read/write ports – poor circuit performance when synthesized

Firstly, are you synthesizing to an FPGA?

This paper from Cypress shows a dual-port RAM as a block diagram. It's not quite clear from there, but the dual-port array in the middle is an array which has a double set of lines: 2 row selects, 2 write column sets, 2 read column sets.

Scaling beyond 2 is difficult because then you need 3, 4 etc sets of wires, and your RAM density goes down as you run out of space for wires.

If you write Verilog which implies more than 2 ports, the synthesis tool will build it out of flops with multiplexors on the front, consuming far more space than RAM cells.

Why do you actually need multiple ports? How large a RAM do you want? Building a memory arbitrator on the front of a normal RAM may be the solution you want.

Best Answer

Related Solutions

Electronic – Is making a D flip flop with asynchronous level triggered reset possible

Electronic – Verilog memory designs with multiple read/write ports – poor circuit performance when synthesized

Related Topic