Electronic – Is making a D flip flop with asynchronous level triggered reset possible

flipflopverilog

I am starting to learn verilog coding in college and didn't have that much of a problem till now. I think I have the basics down perfectly. But I just hit a brick wall with this one. I was experimenting with behavioral modeling and ended up having this problem.

It is easy to make a D flip flop with synchronous level triggered reset like this

always @(posedge clk)
begin
    if(clr) begin
        q <= 1'b0;
    end
    else begin
        q <= d;
    end
end

Or making a D flip flop with synchronous edge triggered reset like this

always @(posedge clk or posedge clr)
begin
    if(clr) begin
        q <= 1'b0;
    end
    else begin
        q <= d;
    end
end

But how can I make a level triggered but asynchronous reset? I cannot do

always @(posedge clk or clr)

because that would be oring two incompatible types, so an error will be thrown while doing the RTL synthesis. I cannot do

always @(posedge clk)
begin
    q <= d;
end

always @(clr)
begin
    q <= 1'b0;
end

since that would require multiple sources to drive q, again problem at RTL synthesis.

So my question is, is making a D-flip flop with asynchronous level triggered reset possible or not? Both in verilog and in digital logic.

Best Answer

Here's Xilinx's example of a "Flip-Flop with Negative Edge Clock and Asynchronous Reset": 

always @(negedge C or posedge CLR)
    begin
        if (CLR)
            Q <= 1’b0;
        else
            Q <= D;
    end

(Source: Synthesis and Simulation Design Guide, UG626, Oct 19, 2011)

Notice that this is basically the same as your second example (except using the opposite clock edge). And in fact this is a level-sensitive clear, not an edge-sensitive clear, because if clear is held high, the output will continue to be held low, even if new clock edges arrive and/or the D input changes.

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