Memory bandwidth for DRAM like DDR3-1600 / PC-12800 is a function (product) of memory frequency (1600 MHz) and memory bus characteristics (width and number of channels). But memory also has timings (for example, 11-11-11, measured in cycles). So is it true that the value of memory bandwidth (12800 MB/s) is unreachable unless timings for that memory equal 0 (zero), that is unreal?
Electronic – Is memory bandwidth advertised for DRAM (like 12800 MB/s for PC-12800) ever achievable
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A DDR memory device actually consists of two distinct components:
1: A series of memory arrays composed mostly of capacitors, which are written to and read from using a very wide bank of differential amplifiers. This is fundamentally an analogue circuit, surprisingly enough.
2: An interface buffer, which allows the hundreds or thousands of individual bits produced by a single memory-array read cycle to be interfaced to a reasonable number of data lines to the Northbridge or CPU. Several cycles on the external interface are needed to transmit the data in the buffer.
In general, the feature size of semiconductor technology decreases over time as manufacturing technology is refined. This has different effects in the above two components.
For the memory array, the differential amplifiers become more sensitive and the individual capacitors become smaller. This allows a larger array to be constructed in the same die area, reading out more bits per cycle. The speed of the array remains roughly the same, however.
For the interface buffer, some of the data paths become shorter and therefore faster, required voltage swings reduce, and there is now space for better skew-correction, clock recovery, etc. This permits higher external signalling speeds within a reasonable power and area budget. The original DDR RAM simply transmitted data on both the rising and falling edges of the clock signal, instead of only on the rising edge as SDRAM did. More recent versions effectively multiply the basic clock signal as well.
This "basic clock signal" usually works out to around 200MHz in mainstream products of each generation, though faster and slower devices are also available. In original DDR, a 200MHz clock meant 400 MT/s, and was often described as 400MHz (or DDR-400) though the highest frequency signal is actually 200MHz. In DDR2, the basic clock is doubled using a PLL at both ends of the interface, so the actual clock rate is 400MHz and there are 800 MT/s. In DDR3 the clock is quadrupled and in DDR4 it is octupled, giving typically 3200 MT/s today. As you can imagine, the timing relative to the clock edges has to be controlled very carefully.
Since the memory arrays themselves haven't changed much in speed, these higher interface speeds come with increased "column strobe latency" (CL) figures. These describe how many transfer cycles elapse between providing the address and receiving the data, and are used to accommodate the limited speed of the memory arrays relative to the interface bus.
One of the things that the basic clock controls more-or-less directly, rather than through a PLL, is the self-refresh cycle of the memory arrays. Using capacitors to store bits is very space-efficient, but the charge leaks out of them rather easily and weakens the indication within a few tens of milliseconds, so the memory arrays must constantly cycle through their contents, reading and re-writing them to ensure they remain valid.
In some cases it is possible to replace DRAM with SRAM, by adding some logic to latch the row address. Whether this will work in a particular circuit depends on the timing of the RAS, CAS, and /WR signals and how the SRAM responds to them. 1 bit DRAMs have separate data input and output pins. If these are not tied together in the circuit then you may also need a Tri-State buffer to bridge between them. Getting the timing right could be tricky.
Here are two examples that work:-
SRAM replacement for lower 16K ← ZX Spectrum
SRAM replacement for TMS99x8 VRAM
You may be able to use higher capacity DRAMs provided that they are compatible - compare their data datasheets to make sure. The main things to watch out for are RAS/CAS timing (Fast Page Mode, EDO etc.) and refresh requirements.
However replacing the the faulty DRAMs with correct equivalents would be much easier and more likely to succeed. Although these older DRAMs are no longer manufactured, many are still available on the second hand market - usually selling at much cheaper prices than when new.
You may not have found what you want because you haven't searched all the equivalent part numbers. eg. '41464' is equivalent to '4464'. Here are some selling on eBay right now:-
Just be aware that these chips may be refurbished and possibly remarked with different parts numbers. Usually they are equivalent, but sometimes not (I bought some 'MCM2114P20 1kx4 SRAM' chips that are actually BU2114F 8 bit shift registers!).
Best Answer
Well, you're never going to get that exactly. That's the theoretical max bandwidth. However, you can get pretty close. DRAM is set up so that rather large blocks can be read out sequentially with no wait states. Well, you might need some wait states to set it up and a few to move to the next block, but within the block it will transfer at the full rate. Generally your CPU will read or write a whole cache line at once anyway, not just a couple of words. This is a tradeoff between sequential access and completely random access, but it usually works well because a good portion of memory reads and writes are sequential.