In other words: if we swap A and B, will Q behave exactly the same in DC and transient analysis?
Electronic – Is the NAND logic gate perfectly symmetrical
cmosdigital-logiclogic-gatesnandspice
Related Solutions
An alternate approach is given.
simulate this circuit – Schematic created using CircuitLab
The schematic represents the function: $$Y = \overline{ABC} = \overline{\overline{\overline{AB}} C}$$
If you draw the two inputs (A,B) and output (C) with their relative timings you should be able to get an idea of what is happening.
Suppose T is the period of the square wave and dT is the delay. As dT changes the output waveform maintains its frequency but alters the mark/space ratio.
If dT = T/2 (exactly 180 out of phase) the output goes HIGH (inputs are either 1,0 or 0,1 so output is 1) with no clock output!
What happens to the output in the interval T/2 < dT <= T?
Best Answer
There will be a very small difference in that circuit because of the differences in VGS in the N stack while the circuit is sinking current during switching. M1 will be marginally slower than M2 under some conditions.
There are however likely to be other factors, say in how the circuit is laid out, that will have an equally large effect.
Define perfect. Much of what we do in EE is about modelling. The model is never perfect and at most levels of abstraction the behaviour of this circuit would be considered to be symmetrical. If we let very small differences in a circuit that typically would include tens of these gates effect us we will never get anything done.