Looks good and you may just get lucky with that layout.
Being an engineer, luck is usually not a method I rely on :-) So let me show you what I would do:
1) Define the PCB stackup. Looks like you are on a 4-layer stackup, but we need to know material and thickness of laminate/prepreg etc.
2) Calculate trace widths to give you 50R on all layers. Your traces looks wide, but you didn't give your stackup so they may be okay. I would worry a bit about crosstalk though if those traces really are 50R (because I then know that they are far from your reference plane, which increases crosstalk).
3) Engineer a great low impedance power delivery network (PDN). I read between the lines that you have two planes for power and ground - which is a really good idea. I would use my tool at pdntool.com to select the right capacitor combination. And use the knowledge that bypass capacitor location is fairly unimportant. So the caps would be placed last so the don't interfere with the routing.
4) Repeat this for your Vtt supply. The termination voltage is being constantly pulled in both directions, so it needs a low impedance as well. With DDR1 on a low layer count board, Vtt ripple is a common problem (and make sure Vref is not connected to Vtt!!!). This would usually require a Vtt island with sufficient bypass. Remember about half the ripple on Vtt will be present as noise on top of any input signal terminated to Vtt.
5) Do some quick IBIS simulations to find a trace separation that gives you acceptable crosstalk. Use Hyperlynx, SigXplorer or some such tool for this. Or get someone to do it for you.
6) Do your timing analysis to find the acceptable tolerance on trace length matching (don't overdo length matching - just keep within your calculated tolerance).
7) Document the above in a nice document and call a peer review - this is a great time to find errors. You could also post that here and ask for problems in your reasoning.
8) Enter everything as routing rules in your CAD tool and do that layout. Remember with a well engineered PDN and 50R on all layers your via count is irrelevant. Also if you just route your differential clock as two 50R traces of same length (within half a rise-time or so), you need not treat them special.
For inspiration you can also look at the layout examples on the JEDEC website.
Hope this helps - feel free to ask more questions.
According to the data sheet, the 3 RGB LEDs are electrically separate. This means that you can connect them in series, using a higher voltage with fewer resistors and transistors. Nick Alexeyev's answer then applies. Assuming a 36 volt power supply, and strings of 8 for green and blue, 16 for red, and 24 for IR, total is 18 channels. I would not go with Nick's suggestion of 48v/12x strings for green and blue, since there isn't enough excess voltage for the limiting resistors to operate reliably, particularly with the Vf variations given in the data sheet. I'd expect that you'd need to measure the voltage drop of each string and tailor the limit resistor values accordingly.
What I think you've missed is power. Assuming 20mA for each LED, total power is 3.6 watts each for green and blue, 2.3 watts for red, and 1.5 watts for IR. Total power is 11 watts in the LEDs. I have no idea how you're going to heatsink this. Well, I do, but it involves using a beryllium oxide substrate for your LED PC board, bonded either to a pretty hefty heat sink, or maybe a TEC cooler. You want the LEDs to run as cool as possible for better lifetime. But trying to do it with FR4 is asking for early death of your LEDs. Similarly, you would also need to calculate the dissipation in your limiting resistors, although for the values I've given I'd expect total dissipation in the 4-5 watt range, and this can be handled with forced air cooling. And with the cooling requirements indicating a certain amount of increased size, I don't think you really need to worry about minimizing the driver board size, although at 18 channels you shouldn't have much difficulty.
/MFG_UMFT601X-B.jpg){kind=link}
Best Answer
People use SMD resistor arrays all the time. They are easy to find on Digi-Key, Mouser, or any other place. The FTDI reference design uses 4xR arrays. Why do you question their advice?
There is always a trade-off. See above. Why don't you take their reference design as a guide?
Termination on the other end depends on input impedance of the link "partner". If this is a FPGA, good ones usually have configurable controlled impedance, so you might need no termination at all if the FPGA configuration is right.
More, from the FTDI datasheet (looking at VIH/VIL at specified drive current) it looks like their driver impedance is about 75 Ω. If you try to target your your traces for 70-80 Ω (which should be easier than 50 Ω) and don't use a controlled-impedance connector in between, you might need no series termination at all.