Electronic – LM3485 current limiter (\$R_{adj}\$) value selection

In addtion to the concerns brought up in the comments (incorrect P-FET polarity, no catch diode/MOSFET), I have some at-a-quick-glance concerns:

• The microcontroller won't be able to drive the gate of Q1 very hard (usually GPIO pins can only source a few milliamps) so your turn-on and turn-off will be very slow. This will limit how well your high-side switch will behave.

• You don't have a gate-to-source resistor on Q1, so you're solely dependent on the GPIO keeping the MOSFET on or off. If the GPIO pin goes high-impedance, the MOSFET may turn itself on if the gate picks up a charge from the environment.

• If your 70R P-channel gate resistor is solidly on (if Q1 is saturated), it's going to burn

  \$ D \cdot \dfrac{(16V)^2}{70 \Omega} = D \cdot 3.65W\$

  which is crazy high power since D is going to be high (input is close to output). Also, the 225mA or so that will flow will also be burned in Q1, which isn't healthy since it's a relatively small device.

  (You need \$V_{GS}\$ of around 4V to draw ~400mA through Q1, and you need \$V_{GS}\$ of -7.5V for 40A in Q4).

  • Your purely resistive feedback network is a bad idea. You really need some compensation and/or filtering. Your comparator will be hyper-fast and could react to switching noise, pickup, ripple, etc. - since you don't seem to be using an error amplifier with compensation to control the gain and phase, you're going to need some cap across R5 (and some luck).

  • You don't have any current monitoring or over-current protection in your power train.

  • You don't have any over-voltage protection in your power train.

  • You don't have any over-temperature protection in your power train.

  • You don't have input reverse-polarity protection and an input fuse in your power train. Big no-no, especially when the source is battery-based (big short-circuit sourcing capability).

This is a simpler project if you use an off-the-shelf analog synchronous buck controller. I don't understand why you would want to use the ATtiny for this.

That being said, this isn't a simple project by any stretch. Your schematic is largely incomplete and lacks basic safety protection that any power supply (especially ones that run at high power levels like yours) will need.

Think about your requirements, calculate all the losses, design in some protections and come back with rev. 2.

The 30% (some data sheets say 40%) is a trade-off between inductor size, ripple current, error sense performance and efficiency. Note that the ripple current is not the same as output ripple voltage. The lower the ripple current you desire, the larger the inductance you need.

The larger the inductor, the higher the DC winding losses (for a given style of inductor) or the larger, physically, the device is.

The switching frequency is also a trade-off. A higher switching frequency leads to a smaller inductor requirement, but increases the losses in the switching elements (usually MOSFETS) due to gate capacitance charge / discharge occurring more often. Indeed, this is why switch FETs are optimised for total gate charge and sync FETs are optimised for Rds(on).

The switching frequency (at least the maximum) is determined to a large extent on the performance of the error amplifier and internal modulator and the added complexity of loop compensation for a circuit with wider bandwidth (i.e. there is gain in the loop to a higher frequency, adding effort for externally compensated designs to ensure the loop remains stable at all possible loads).

Higher frequency operation actually makes the output ripple noise easier to filter in the majority of cases, and high loop bandwidth increases the transient performance of the design, so there are both pros and cons attached to switching frequency.

Ripple current in the inductor and transient currents in the switching FETs can induce large noise spikes in the immediate vicinity of the devices, and this is one reason why layout can be quite challenging for switch-mode devices. Poor layout practices are (in my experience, at least) the primary source of noise being induced where it is undesirable.

The ripple is filtered by the output capacitors, and just how much filtering you get depends on a number of factors, noting that the output filter devices are part of the loop compensation analysis.

There are some excellent resources available to understand the trade-offs in switching regulator design, and Switching Regulators for Poets by Jim Williams is often cited as one of the best available.

Loop analysis (for a particular type of loop) and compensation is covered thoroughly in AN-76 from Linear Technology.

There are, of course, such resources available from many manufacturers, such as Texas Instruments

This is a huge area of study, and I commend you to manufacturers application notes (even though they may look at specific devices on occasion) for detailed information and explanations of the various architectures and topologies that switch-mode devices can have.