There are a few mistakes in the question:
- The original reference design called for 4K7 (4.7K) ohm resistor for R1. This should fix your problem. Note that the specs for hfe (DC current gain) are typical and not guaranteed, so you need to design in some margin (as was done in the reference design).
- There was a mistake in your equation: vc=(12.38−25m∗47k) and later vc=(12.38−25m∗10k). You need to use the value of R2 (1K in your schematic). Also note that the result of the calculation is negative but the actual value of Vc will not go below Vce-sat (all other things being correct, a negative value would indicate saturation and the actual Ic would be lower.
The specified 4.7K resistor for R1 should correct the problem.
Edit:
One way of working out an appropriate value for R1 would be to work backwards from the collector. Assuming you want R2 to be 1K (for adequate edge rates for the IGBT in this case):
- Calculate the saturation current (we'll ignore Vce and call it 0) ... Ic = 12V / 1000 ohm = 0.012A
- Calculate the necessary base current with some margin (we will use hfe=10 to be safe) ... Ib = Ic / hfe = 0.0012A
- Calculate the value for R1 needed to achieve the above base current (0.7V assumed for Vbe) ... R1(max) = (12V -0.7V) / 0.0012A = 9417 ohm. With some more margin (allows for temperature, capacitor leakage or ?), 4.7K is a good choice for R1.
Forgive me for using another schematic for common base configuration, but I found it more understandable in education purpose.
First, voltage gain:\$A_{v}=\frac{u_{iz}}{u_{ul}}\$
Usual way to deal with this fraction is to derive the expression for both of the voltages separately and then evaluate.
Output voltage is equal to: \$u_{iz}= -h_{fe}\cdot i_b \cdot R_c ||R_T\$
Input voltage is equal to: \$u_{ul}=i_{ul}\cdot R_E = -i_b \cdot r_{be}\$. Notice the sign of the current and why we took \$-i_b\$(because the current flows in the negative terminal of the predefined voltage \$u_{ul}\$)
Therefore, voltage gain is equal to: \$A_{v}=\frac{u_{iz}}{u_{ul}}=\frac{-h_{fe}\cdot i_b \cdot R_C||R_T}{-i_b \cdot R_E}=h_{fe}\frac{R_C||R_T}{R_E}\$
Current gain is a bit difficult to derive, but don't give up :)
First, we need to see what is the expression for input resistance of the amplifier \$R_{ul}\$ (which is also an important parameter while designing an amplifier)
Input resistance is: \$R_{ul}=\frac{u_{ul}}{i_{ul}}\$
Currents are: \$i_{ul}=i_{Re}+i_e; i_{Re} = \frac{u_{ul}}{R_E}; i_b = - \frac{u_{ul}}{r_{be}}\$
If we apply KCL for node E we have: \$i_e+i_b+h_{fe}i_b=0, i_e=-i_b(1+h_{fe})\$
Expression for input current is: \$i_{ul}=i_{Re}+i_e=i_{Re}-i_b(1+h_{fe})=\frac{u_{ul}}{R_E}-(1+h_{fe})=u_{ul}\cdot (\frac{1}{R_E}+\frac{1}{\frac{r_{be}}{1+h_{fe}}})\$
Now when we take a step back and take a look at the input resistance expression:
\$R_{ul}=\frac{u_{ul}}{i_{ul}}=R_E || (\frac{r_{be}}{1+h_{fe}})\$
From the last expression we can notice that the input resistance is equal to 2 resistor in parallel. First one is \$R_E\$ and the second one we can call \$R_{ul}'\$.
We are finally here, \$i_{iz}=\frac{u_{iz}}{R_T}; i_{ul}=\frac{u_{ul}}{R_E || R_{ul}'}\$
Current gain: \$A_{i}=\frac{i_{iz}}{i_{ul}}=\frac{\frac{u_{iz}}{R_T}}{\frac{u_{ul}}{R_E || R_{ul}'}}=\frac{u_{iz}}{u_{ul}} \cdot \frac{R_E || R_{ul}'}{R_T} = A_V \cdot \frac{R_E ||R_{ul}'}{R_T}\$
From here we can see that the current gain of these configuration can never be bigger than 1 and always positive.
I hope everything is clear now!
Best Answer
This can be easily seen from graph below:
There are two load lines: Green with smaller slope and Red with higher slope.
For a given change in \$V_{be}\$, lower slope (green line) will give a corresponding higher change in \$V_{ce}\$, simply because it has less slope. Hence voltage gain is higher, as it is just the ratio \$\frac{\Delta V_{ce}}{\Delta V_{be}}\$.
By the same reasoning, a line with higher slope (red line) will give more current gain simply because change in the output current \$I_c\$ will be more for higher slope.
This can also be seen analytically as follows: $$A_v = g_m(R_c||r_{out})$$ Here, \$r_{out}\$ is the output impedance of the transistor (along with its degeneration). Since, \$r_{out}\$ is very high, $$A_v \approx g_mR_c$$ Thus, higher \$R_c\$ implies higher voltage gain. $$A_i = \beta \frac{r_{out}}{r_{out}+R_c}$$ Clearly, if \$R_{c}\$ is very small, $$A_i \approx \beta,$$ which is the highest current gain.
In response to LvW's Comment
Assuming, \$R_E\$ is zero, the following is the relation between change in \$V_{be}\$ and \$I_b\$: $$v_b = \frac{(\beta+1)i_b}{g_m} \implies i_b = \frac{g_mv_b}{(\beta+1)}$$ Thus, change in base current is proportional to the change in base emitter voltage. Thus, the current gain can be compared just by the change in collector current since the change in base current is the same for the two lines.