I'm trying to make a level 2 simulation of a voltage buffer made by a CMOS circuit:
Buffer http://www.ele.uri.edu/images/Gif/buff_tran.gif
For this, I have been told to use level 2 CNM25 technology Spice models for the transistors, and I have been given the models:
.model NEWPMOS PMOS (LEVEL=2 TOX = 380E-10 VTO = -1.139 NSUB = 1.355E16 UO = 212.7 UCRIT = 1E4 UEXP = .1159 NFS = 662.4E9 WD = .4268E-6 DELTA = 1.824 RS = 134.9 LD = .8101E-6 XJ = 2.783E-9 VMAX = 120.3E3 NEFF = .06665 CJ = 3.816E-4 MJ = .3499 CJSW = 7.384E-10 MJSW = .3916 PB = .56)
.model NEWNMOS NMOS (LEVEL=2 TOX = 380E-10 VTO = .9418 NSUB = 2.639E16 UO = 648.2 UCRIT = 1E4 UEXP = .06857 NFS = 710.8E9 WD = .4086E-6 DELTA = 2.2 RS = 93.77 LD = .9132E-6 XJ = .0824E-6 VMAX = 59.62E3 NEFF = 1.479 CJ = 3.495E-4 MJ = .3950 CJSW = 5.952E-10 MJSW = .2941 PB = .65)
When I simulate the circuit, the output signal has rising peaks at the edges when the input signal goes from high to low and from low to high:
When I zoom in into the peaks, they are really weird and have a 400mV amplitude which I don't know where it comes from.
Is this suppose to happen or is there something wrong with the models? or, if it is correct, why does these peaks occur?
Best Answer
These look like charge injection from the overlap capacitance of gate to S/D. If you overlay the intermediate node output (the output from the first inverter) you will find that these edges are related to the the signal swing of this internal node.
As the Output is swinging from low to high the internal node must first swing from high to low and some of the edge will couple into the output signal. That 's why it looks odd, it appears to be happening before the the signal switches.
I grabbed this pictures from ITU website in which there is a discussion of capacitances of a MOSFET.
This picture is for a MOSFET when it is turned off, when on, there will be a Gate to channel cap and a channel to bulk cap.