Electronic – LTspice simulation doesn’t work, what am I doing wrong

ltspicesimulation

We were talking about this simple ramp generator: What would be the simplest BJT based *linear* ramp generator?
and talking about simulation. So I downloaded LTspice drew up the circuit and started to measure. But it's not working! Here, the green trace is at the collectors of Q1 and Q2, the blue trace is on the PULSE generator to verify that I have it set up right.

When I only measure at the collectors of Q1, Q2, I get this weird line:

Here is the ramp.asc file. I must be doing something really stupid. Who can spot the error?

Version 4
SHEET 1 1196 680
WIRE -64 -144 -240 -144
WIRE 96 -144 -64 -144
WIRE 96 -32 96 -64
WIRE -240 0 -240 -144
WIRE -64 16 -64 -64
WIRE 32 16 -64 16
WIRE 96 96 96 64
WIRE 352 96 96 96
WIRE -64 128 -64 16
WIRE 96 144 96 96
WIRE 352 144 352 96
WIRE 576 192 496 192
WIRE -240 288 -240 80
WIRE -64 288 -64 208
WIRE -64 288 -240 288
WIRE 96 288 96 208
WIRE 96 288 -64 288
WIRE 352 288 352 240
WIRE 352 288 96 288
WIRE 576 288 576 272
WIRE 576 288 352 288
WIRE -64 304 -64 288
WIRE 800 464 768 464
FLAG -64 304 0
SYMBOL res -80 -160 R0
SYMATTR InstName R1
SYMATTR Value 2k
SYMBOL res -80 112 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 80 -160 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 512 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL cap 80 144 R0
SYMATTR InstName C1
SYMATTR Value 33 pF
SYMBOL pnp 32 64 M180
SYMATTR InstName Q1
SYMATTR Value BC556B
SYMBOL npn 416 144 M0
WINDOW 3 57 67 Left 2
SYMATTR InstName Q2
SYMATTR Value BC546B
SYMBOL voltage -240 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 576 176 R0
WINDOW 3 44 86 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 0 0 .005 .01 100)
TEXT -274 328 Left 2 !.tran 0.05

Best Answer

I can't reproduce your waveforms by recreating the exact schematic from your 1st picture. Have you modified some settings? I used a .step to cycle between the values of 33p (your value, black trace) and 33n (blue trace) for C1, mostly to show the differences, but also to show that it works (though not as you'd expect):

I am considering the deafult models from the default installation; if you modified, in any way, the models for the transistors, then the results of your simulation may be different. Also, there is no need to specify the number of periods for the PULSE() source, unless you really need a certain number of them; 0 means the pulses repeat forever.

The "netlist" you provided does not help. As @SpehroPefhany mentioned in the comments, you need to copy-paste the contents of the .asc file. This is a simple schematic, so it didn't take long to recreate, but if you had a larger one... Still, for the case where it would indeed not work, there are a few possible solutions.

The solver first will try to solve for the operation point, since you have provided no flags. This means that, when you hit "run", the circuit should have been running since the beginning of time, having had time to settle all the possible transients, to a specific operating point -- the one you see at the simulation start. For that to happen, inductors are considered short-circuits and capacitors open-circuits. What you show in your plot is the voltage across the capacitor starting at ~4.78 V. That makes sense if you consider the resistive divider formed by R[1:3], and the static resistances of the transistor polarized by those resistors.

If you want to see the "normal" behaviour (i.e. what you expect to see), you have to tell the solver, because it cannot read minds. You have a few choices:

Add the startup flag: .tran 0.05 startup. This makes DC sources to ramp up in a fraction of the total simulation time (10 us, IIRC). This way, the beginning of the simulation will see the supply voltage at t=0 as 0 V, thus the capacitor will also start from zero.
Add initial conditions. This will force the solver to consider a custom value for the voltage at that node. This can be done in two ways:

global condition, with a SPICE directive: .ic v(x)=<value> (considering x as the label for that node). For your case, <value> can be 0.
local condition, by adding ic=<value> to the capacitor, next to its value (also 0 for your case).

Adding the uic flag. This forces the solver to avoid calculating the operation point, and start everything from zero. That is, it considers the beginning of time starts with your pressing "run". From that moment on, it will calculate and show all the values as they progress through the simulation. Use this option with care, since it can mean the difference between simulating for a minute vs an hour. In this case, it's a very simple circuit.

There may be other, more exotic ways, such as an actual circuitry (a VCSW, perhaps) that forces the capacitor to be shorted and opening up after the simulation is started, or adding a simple, minor pulsed current source that forces zero current prior to simulation and a very narrow pulse after, to kick-start the voltages (this is mostly used for oscillators, but it works here, too), but they'll only add extra burden to the matrix solver.

Now that you posted the code for the .asc file, that gave me a good chuckle. My eyes must be getting worse than I thought, because you assigned 33<space>pF as the value for the capacitor. I'm surprised you didn't say anything about the error log popping up, that would have simplified things greatly (not to mention it kinda screams about the cause of the error). The very first lines are:

Error on line 6 : c1 n004 0 33 pf
     Unknown parameter "pf"

That <space> doesn't belong between a numerical value and its metric prefix, because the parser will interpret that as two values, 33 and pF. Since it doesn't recognize pF as a keyword or a flag, and it can't evaluate it (not lastly because of the lack of curly braces or single quotes), it interprets only the first value, 33, thus considering the capacitor as 33 Farad, and complains about the rest in the error log. That's why you see an almost pure integrator behaviour there.

Whatever's written above still stands, though, with the addition that the circuit will function correctly without any of the settings, since V2 is actively contributing to the discharging of the capacitor. But you can see how, even in my picture, it starts from ~4.78 V, because of the explanation above.

BTW, there's nothing wrong by writing units (F, uH, kOhm, etc), LTspice will ignore them, but it's useless, unless you like seeing the units.

Related Solutions

Electronic – LTSpice power supply simulation: what is wrong with it

There are a few problems with this schematic

1) You are using an ideal voltage source, You may want to add some inductance and resistance to simulate wires. Mains power is not infinite, and neither is the current from a transformer. Your transformer is going to have a lag on power that it can deliver, you should probably simulate this. Another thing to watch out for is transformer saturation. (unless your not getting power from AC mains)

2) As the other answers say, you have a huge capacitor, is throwing more capacitance at the problem going to be a good solution? If the current is too high, then you need to change the design, not the parameters of the design. At these current levels you should probably use a DC to DC instead of a vreg unless price is an important consideration. You are going to burn up lots of power. Its better to put smaller amounts of current at a higher voltage through the rectifier You can get cheap DC to DC regulators that are 780X drop in compatible that will handle 1 amp, you can parallel them if you need more current. If that doesn't work then go find a DC to DC IC. Have you considered a AC to DC power supply such as a "wall wart"? People make these things for less than 20$.

Electronic – LTSpice D flip-flop not working

If you go to the LTspice help and navigate to "Special Functions" you'll see a list of parameters that can be selected for the digital components, including the Dflop.

Your shift register didn't work because it had no output rise or fall time associated with it, so everything was happening all at once!

Also, the digital stuff defaults to a Vcc of 1 volt.

I've redrawn your schematic so everything starts cleared, Vcc is 5 volts, and put some delay into the Dflops, and now it works. :)

If you right-click on any of the dflops, that'll bring up the attribute editor, which will show their edited (non-default) parameters, specifically:

SpiceLine = Vhigh 5 Trise 10n

and will allow you to modify any of the component's editable attributes.

Here's the schematic and the plot, which I edited to look like a timing diagram:

and here's the circuit list:

Version 4
SHEET 1 1732 752
WIRE 48 -144 -256 -144
WIRE 352 -144 48 -144
WIRE 656 -144 352 -144
WIRE 864 -144 656 -144
WIRE 1104 -144 864 -144
WIRE 1360 -144 1104 -144
WIRE 1616 -144 1360 -144
WIRE -128 -64 -368 -64
WIRE 176 -64 -64 -64
WIRE 480 -64 240 -64
WIRE 784 -64 544 -64
WIRE 864 -64 864 -144
WIRE -256 0 -256 -144
WIRE 48 0 48 -144
WIRE 352 0 352 -144
WIRE 656 0 656 -144
WIRE 1104 0 1104 -144
WIRE 1360 0 1360 -144
WIRE 1616 0 1616 -144
WIRE -368 48 -368 -64
WIRE -336 48 -368 48
WIRE -160 48 -176 48
WIRE -64 48 -64 -64
WIRE -32 48 -64 48
WIRE 144 48 128 48
WIRE 240 48 240 -64
WIRE 272 48 240 48
WIRE 448 48 432 48
WIRE 544 48 544 -64
WIRE 576 48 544 48
WIRE 1024 48 736 48
WIRE 1280 48 1184 48
WIRE 1536 48 1440 48
WIRE 1728 48 1696 48
WIRE -336 96 -368 96
WIRE -128 96 -128 -64
WIRE -128 96 -160 96
WIRE -32 96 -128 96
WIRE 176 96 176 -64
WIRE 176 96 144 96
WIRE 272 96 176 96
WIRE 480 96 480 -64
WIRE 480 96 448 96
WIRE 576 96 480 96
WIRE 784 96 784 -64
WIRE 784 96 752 96
WIRE 1024 96 992 96
WIRE 1280 96 1248 96
WIRE 1536 96 1504 96
WIRE -368 208 -368 96
WIRE 992 208 992 96
WIRE 992 208 -368 208
WIRE 1248 208 1248 96
WIRE 1248 208 992 208
WIRE 1504 208 1504 96
WIRE 1504 208 1248 208
WIRE -256 288 -256 144
WIRE 48 288 48 144
WIRE 48 288 -256 288
WIRE 352 288 352 144
WIRE 352 288 48 288
WIRE 656 288 656 144
WIRE 656 288 352 288
WIRE 1104 288 1104 144
WIRE 1104 288 656 288
WIRE 1360 288 1360 144
WIRE 1360 288 1104 288
WIRE 1616 288 1616 144
WIRE 1616 288 1360 288
WIRE -368 336 -368 208
WIRE -256 336 -256 288
WIRE -368 448 -368 416
WIRE -256 448 -256 416
WIRE -256 448 -368 448
WIRE -368 512 -368 448
FLAG -368 512 0
FLAG 864 -64 0
SYMBOL voltage -368 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 86 297 Invisible 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1u 5n 5n 0.5u 1u)
SYMBOL voltage -256 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 86 297 Invisible 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 50n 50n 100n)
SYMBOL Digital\\dflop -256 0 R0
SYMATTR InstName A1
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 48 0 R0
SYMATTR InstName A2
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 352 0 R0
SYMATTR InstName A3
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 656 0 R0
SYMATTR InstName A4
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1104 0 R0
SYMATTR InstName A5
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1360 0 R0
SYMATTR InstName A6
SYMATTR SpiceLine Vhigh 5 Trise 10n
SYMBOL Digital\\dflop 1616 0 R0
SYMATTR InstName A7
SYMATTR SpiceLine Vhigh 5 Trise 10n
TEXT -352 480 Left 2 !.tran 0 30us 0

Best Answer

Related Solutions

Electronic – LTSpice power supply simulation: what is wrong with it

Electronic – LTSpice D flip-flop not working

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