If you got a board which had a VGA connector (or rigged one up, with some resistors) you might find it simpler to start by driving an LCD with that interface, and then work up to a bare one.
Block memory inside an FPGA tends to be easier to work with than SDRAM, and is dual port which simplifies access, but of course it's more limited. Still, it could be worthwhile to start that way and then add the SDRAM complexity. A higher gate count FPGA would typically have more block ram, too.
Of course you can start by drawing some bars on the screen just using a state machine or counter without any frame buffer at all.
An oscilloscope would be a huge help.
Many LCDs actually aren't that picky about frequency, so while you can use the clock generators to get it just right, you may not need to.
An issue not to overlook is the practical task of securely cabling the LCD to the FPGA board - with 24 bit color there's a bit of work there unless you really luck out and you can just plug one into the other.
I think the second line should be
constant LOWER_BOUND : natural := 7;
above. (OK, it is now! :-) But anyway...
welcome to a language with a proper type system! Learn to use it, and you will love it. Or learn to fight it, and you will hate it. Your choice...
What you are looking for is either
type Field_Range is range UPPER_BOUND downto LOWER_BOUND;
or
subtype Field_Range is Natural range UPPER_BOUND downto LOWER_BOUND;
according to whether you want type safety, or easy mixing of Field_Range with other integer quantities.
Either way you can say
Field : Array(Field_Range) of Something;
for i in Field_Range loop
...
end loop
and (almost!) never worry about bounds errors again.
What is the difference between Type and Subtype?
That'll take a little learning, but here's a start:
if you have the following,
constant N : Natural := 7;
constant F : Field_Range := N;
the subtype will allow it, the new type will not, you would need to convert:
constant F : Field_Range := Field_Range(N);
Best Answer
LVDS_XX only gives you the voltage of the power rail for that IO bank. LVDS_25 is only allowed on a 2.5V bank, LVDS_18 is only allowed on a 1.8V bank, etc. The actual voltage levels are just "LVDS level."
The information in this Answer specifically targets Xilinx, because that's what the question refers to and that's what I'm experienced with. To apply this to other FPGAs or devices, just check the input and output specs on the datasheet.
LVDS common mode voltage is around 1.25V. See the blue circles in the below tables.
LVDS differential voltage is around 350mV. See the red circles in the below tables.
To know if a driver is compatible with a given receiver, check the levels. If the output min is above the input min, and the output max is below the input max, you're fine. Check the whole datasheet for other constraints, such as max IO-to-Vsupply difference (the Xilinx datasheet takes this into account).
source
source
NOTE: "LVDS" here is referred to as "LVDS_18" in other contexts.
Information and tables taken from the following sources:
TI: Interfacing Between LVPECL, VML, CML, and LVDS Levels
Xilinx: Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics