Electronic – Making a circuit entirely with 4:1 MUX, 2-input OR gate and NOT gate

digital-logicmultiplexer

I'm stuck on this question for half of a day. Let's say I have this function

That's everything I know about it. Now I must implement it using only 4:1 MUX, 2-input OR gate and NOT gate. I've tried to look at the truth table and create a circuit, but it uses a constant and AND gate, which is forbidden in my case.

Is there any convenient way to solve this problem, instead of trying to guess it?

Best Answer

You're nearly there. Your solution uses the mux to select rows of the K map and then you generate the correct function for each row.

If you instead use the mux to select columns of the K map — i.e., connect "y" and "z" to the select lines — then you can generate the function for each column: column zero is just "x" and column 1 is "w+x". In other words, the only other gate you need is the OR gate. The NOT must have been thrown in as a red herring.

Related Solutions

Electronic – the minimum number of NOR gates needed to implement a 2-input multiplexer

You can build the mux with 4 NOR gates, too. It doesn't require extra inverters on the inputs and outputs, if that's what you were doing. Note that the sense of the "select" input is inverted, so you need to swap the "A" and "B" inputs to compensate.

Electrical – How to convert multiple Karnaugh maps into a logic gate circuit

Do I combine all of the expressions (as in W+X+Y+Z or WXYZ)

No. What the equations show you are how to derive outputs for four separate pins. If you wanted to combine the four pins you should have done it earlier when coming up with the Karnaugh map (the Karnaugh map would then only have one output instead of four).

First step, treat the four as four separate circuits:

A ─┬───────────────┐
   │               │
B ──┬─[NOT]────────[AND]┐
   ││              │    │
C ────[NOT]──┬─────┘    [OR]── W
   ││        └[OR]─┐    │
D ────────────┘    │    │
   │└──────────────[AND]┘
   └──[NOT]────────┘

 .... implementation of other circuits left as homework

A ──[NOT]────────┐
                 │
B ──[NOT]──┐     [OR]─┐
           [AND]─┘    │
C ──[NOT]──┘          [AND]── Z
                      │
D ────────────────────┘

Second step, join A to A, B to B etc.. This is obvious because obviously A is the same as A etc.

A ─┬────┬───────────────┐
   │    │               │
B ──┬────┬─[NOT]────────[AND]┐
   ││   ││              │    │
C ───┬─────[NOT]──┬─────┘    [OR]── W
   │││  ││        └[OR]─┐    │
D ────┬────────────┘    │    │
   ││││ │└──────────────[AND]┘
   ││││ └──[NOT]────────┘
   ││││
   └───────[NOT]────────┐
    │││                 │
    └──────[NOT]──┐     [OR]─┐
     ││           [AND]─┘    │
     └─────[NOT]──┘          [AND]─ Z
      │                      │
      └──────────────────────┘

 .... implementation of other circuits left as homework

The circuit should be working at this point but if you're paying attention you may notice that some parts of the W and Z circuits are sharing the same logic. For example, we're using NOT on B and C twice. The next (optional) step is to refactor the circuit and remove redundant/repeated subcircuits and components:

A ───┬──────────────────┐
     │                  │
B ────┬─[NOT]──┬────────[AND]┐
     ││        │        │    │
C ──────[NOT]───┬──┬────┘    [OR]── W
     ││        ││  │         │
     ││        ││  [OR]─┐    │
D ─┬───────────────┘    │    │
   │ ││        ││       │    │
   │ │└─────────────────[AND]┘
   │ │         ││       │
   │ └──[NOT]─┬─────────┘
   │          │││
   │          └─────────┐
   │           │└─┐     [OR]─┐
   │           │  [AND]─┘    │
   │           └──┘          [AND]─ Z
   └─────────────────────────┘

 .... implementation of other circuits left as homework

Best Answer

Related Solutions

Electronic – the minimum number of NOR gates needed to implement a 2-input multiplexer

Electrical – How to convert multiple Karnaugh maps into a logic gate circuit

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