What is the meaning and effect of "strong" and "weak" drive shown by (0,1) and (L,H) in VHDL's package ieee.std_logic_1164?
VHDL – Understanding Strong and Weak Drive in VHDL
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What is the meaning and effect of "strong" and "weak" drive shown by (0,1) and (L,H) in VHDL's package ieee.std_logic_1164?
Best Answer
The
ieee.std_logic_1164
package allows two drive strengths.(0,1) are normal drive strength and used for all normal purposes. (L,H) are weak drivers, they are normally used to model pull-up and pull-down resistors.
Formally,
ieee.std_logic_1164
distinguishes between thestd_ulogic
andstd_logic
types, even though they share the same set of values (U,L,H,0,1,X,Z etc).The difference between them is this :
std_ulogic
is an unresolved type. It is an error for astd_ulogic
signal to be driven by two signal sources (like short circuiting 2 wires together - it's usually a mistake) - such errors will be caught (by the compiler) and fixed (by you!) even before you get to simulation.On the other hand,
std_logic
is a resolved type. It is legal to have two or more drivers on a signal. The result is determined by a "resolution function" which looks at all the driving values and combines them into the value you will see on the signal. For example,0
and '1' combine to produceX
(the Unknown state) , andX
and anything else producesX
so that once Unknowns happen, they propagate through the design to show there's a problem.But '0' and 'H' combine to produce '0' (because
H
is weak) and similarly, '1' and 'L' combine to produce '1'. So a strong driver can legally overpower a weak one : no harm done.Let's look at the 'Z' state : it signifies Undriven, or High Impedance (High-Z). Now
Z
andH
combine to produceH
becauseH
, though weak, is still stronger than no driver at all.This is just a brief summary : for all details see a good VHDL book or even the ieee.std_logic_1164 package source code.
So one use of a weak
H
is in the so-called "wired-or" configuration, as used in I2C buses.We are safely combining 4 drivers on the same signal : one I2C master, two slaves, and a permanent weak pullup.