Electronic – MOSFET Terminals in Layout

Model level 3 definition: "Semi-empirical" - a more qualitative model that uses observed operation to define its equations. This dates from 1980 ... Any sort of decent result (i.e. within 10% of reality) would need to use level 5 models (AKA BSIM3). I'd recommend using BSIM 3V3 which is model level 49 in Star-HSPice parlance.

As long as you going to be using out of date models then you should heed your prof and only look at the trends. I suspect that there probably is a reason he said that.

You're dealing with curve fitted results.

Additionally, unless you have parasitic extraction enabled the rail capacitances as you noted are almost certainly not being extracted. The CJSW means Capacitance, Junction Side Wall and is a computed values based upon the width and S/D sizes (as one example). There are excellent SPICE guides that tell you what all the parameters are, I suggest you find and read them.

No, this is not an error. Physically, the source/drain capacitance is the capacitance of the reverse-biased PN junction formed between the NMOS source/drain diffusion and the P substrate (or P well). When two transistors of the same kind (NMOS or PMOS) are connected in series it is often possible to use a single diffused region as both the source of one transistor and the drain of another transistor. In that case, the capacitance of the shared source/drain is not double the capacitance of a single, isolated source or drain.

In the figure you provided it looks like the three series NMOS transistors are assumed to have shared source/drain regions. On the other hand, it looks like the PMOS transistors are assumed to not have shared source/drain regions so each contributes 2C to the capacitance at the output terminal of the gate. In my experience, we usually connected parallel transistors so that the drains were shared whenever possible and left the sources as separate physical diffusions. Since the sources are tied to power or ground anyway there is no benefit in reducing their net capacitance.