Electronic – Multiplexing two SPI Master

"An introduction to asynchronous circuit design" by Davis and Nowick (in particular, Figure 1 and Figure 2 and the nearby text) describes two handshaking protocols as "pervasive". The 4-cycle protocol, aka RZ (return to zero), 4-phase protocol, and level-signaling. And the similar but more complicated to implement 2-cycle protocol, aka transition, 2-phase, or NRZ (non-return to zero) signaling -- which is very similar to the "data strobe encoding" used by SpaceWire and FireWire. Either one sounds like it has most of the features you requested -- it's SPI-like in that there are exactly 4 signals, all 4 signals are one-way (no passive pull-ups), the master can pause the slave indefinitely until it is ready for the next bit from the slave, etc. It also has a feature supercat requested that SPI doesn't have: the slave can pause the master indefinitely until it is ready for the next bit from the master.

I don't know of any chips that have the 4-cycle protocol built in, but it looks like it would be easy to bit-bang on a microcontroller or a CPLD. In fact, it looks like it would be easier to bit-bang than SPI, since (like SPI) the master has no timing requirements, and (unlike SPI) the slave has no timing requirement either.

Is it possible to use the 4-phase protocol for synchronous bit transfers, and somehow build a higher-level protocol on top of that to get the other things supercat wants -- byte alignment, start-of-command frame alignment, attention/busy/idle states, etc?

A "slave" SPI device that controls another slave becomes a master by definition.

If your front panel software is capable of implementing either slave or master roles at different times there is nothing to stop it doing so, provided that the hardware can accomodate the necessary signal flow and the "normal" SPI master does not interfere or "become confused" by the action. ie

• Your masters need to cooperate physically: If two masters try to work at once, or if one master asserts a signal line (eg clock) that affects the ability of the other master to control the same line when desired then "there will be problems".

• Your masters need to cooperate logically: If one master "thinks" it is controlling the bus but the other is also altering the clock or data lines "there will be problems".

From the UART and SPI IC's point of view the physical identity of the master device is unimportant as long as the signal levels and signal flow occurs correctly.