Electronic – N-channel MOSFET connection

I think this is the graph of your datasheet that gives all the information you need:

So assuming this circuit

V_GS is -3V which allows I_D to be up to ca. 0.5 A.

EDIT:
clabacchio is right pointing out that the graph is actually for V_DS = 5V.
Of course a graph for V_DS = 3V would be better, but there isn't one in the datasheet. So the question is: Will the resistance R_DSON be different for very low drain currents?
Looking at Figure 2 ("On-Resistance Variation with Drain Current and Gate Voltage") gives the answer:
it does change vs. I_DS, but only for currents above ca. 0.1 A and: resistance even gets lower (=better) for lower I_DS.

Note that this is not a power converter but effectively a chip that uses a PFET to implement active rectification. As such, the current is intended to flow from the battery to the load when the switch is on. The FET is being used like a diode, making use of the inherent body diode of the part. The chip then turns on the FET to make the diode look more ideal when it should already be on. The chip will turn off the FET quickly when is sees SENSE go higher than Vin. If it didn't, the "diode" would conduct backwards.

The advantage of such a design is that the effective diode has very low forward drop, which is useful when it's in series with a battery since less of the battery power will be wasted. The drawback is that the overall diode has slow reverse recovery time, since the chip has to sense the reverse voltage and then actively shut off the FET. In this case the diode is used for power ORing, so a few µs reverse on time won't matter much.