Electronic – No feasible entries for subprogram “CONV_INTEGER”

testvhdl

I have implemented a simple adder component with two inputs and one output.

port ( A,B :  in std_logic_vector(31 downto 0);
       R   : out std_logic_vector(31 downto 0)
     );

I created a test bench in order to test this component. Then I modified this test bench in order to read the inputs from a text file and in order to write the results to a text file. Currently inputs must be binary strings; similarly, the output is written as a binary string.

Now I would improve this test bench in order to read inputs as integer value from text file. I was able to make this change successfully. But I would also like the output to be written as an integer: in this case, the compiler reports an error on a line of the following source code.

architecture tb4 of tb4_AdderBehav is
  component AdderBehav is
    port ( A,B :  in std_logic_vector(31 downto 0);
           R   : out std_logic_vector(31 downto 0)
       );
  end component;

  signal A,B : std_logic_vector(31 downto 0);
  signal R   : std_logic_vector(31 downto 0);

begin
  dut: AdderBehav port map (A,B,R);

  process
    variable tbInputs, tbOutput : line;
    variable va, vb, vr : integer;
    file data_file : text;
    file result_file : text;

  begin
    file_open(data_file,"dati_int.txt",READ_MODE);
    file_open(result_file,"risultati_int.txt",WRITE_MODE);

    while not endfile(data_file) loop
      readline(data_file,tbInputs); read(tbInputs,va); read(tbInputs,vb);
      A <= conv_std_logic_vector(va, A'length);
      B <= conv_std_logic_vector(vb, B'length);
      wait for 10 ns;
      --vr := conv_integer(R);   -- ERROR: No feasible entries for subprogram "CONV_INTEGER"
      --write(tbOutput,vr);
      write(tbOutput,R);
      writeline(result_file,tbOutput);
    end loop;

    file_close(data_file);
    file_close(result_file);
    wait;
  end process;

end tb4;

Why does the error occur in the source code shown above?
In the source code I have included the following libraries:

ieee.std_logic_1164.all;
ieee.std_logic_textio.all;
ieee.std_logic_arith.all;
ieee.numeric_std.all;
std.textio.all;

Best Answer

The short form answer : first delete the non-standard library ieee.std_logic_arith.all;

It and its std_logic_[un]signed cousins are a mess of slightly ambiguous functions that obscure what your code means and can fail unexpectedly like this example. Does conv_std_logic_vector generate a signed or unsigned representation? Does that depend which libraries you are using? Does conv_integer convert TO an integer, or FROM an integer?

Second, decide what your std_logic_vector quantities represent : signed or unsigned numbers?
You can declare them as signed or unsigned instead (from ieee.numeric_std library). If you MUST keep them as std_logic_vector (WHY?) then you can cast between types via signed(), unsigned(), std_logic_vector().

Then you can replace 

A <= conv_std_logic_vector(va, A'length);
vr := conv_integer(R);

with 

A <= to_unsigned(va, A'length);     -- or to_signed
vr := to_integer(R);
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