I do not understand the following memory map regarding the NVIC registers in Programming Manual for STM32f103 page 129. It says that the offset address for NVIC_IPR0 is 0x300 and that of NVIC_IPR20 is 0x320. I do not understand how is this possible?! I think that the offset for NVIC_IPR20 should be 0x350. Indeed, assuming the registers follow one after another one obtains something like this:
NVIC_IPR0 -> 0x300
NVIC_IPR1 -> 0x304
NVIC_IPR2 -> 0x308
etc.
NVIC_IPR20 -> 0x350
What am I doing wrong?
Best Answer
You're correct -- that looks like a typo. The offset for that register should be
0x350
.The CMSIS header file (
core_cm3.h
) avoids the issue entirely by definingNVIC->IP
as an array of bytes, not of 32-bit words:This documentation error was probably the result of confusion between the byte-wise structure used by ARM and the 32-bit structure used by ST.