Electronic – Base addresses and offset values for registers, STM32 documentation

datasheetinterruptsmicrocontrollerstm32

See the document here.

From page 193:

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This table looks like stating that the base address for NVIC block is 0xE000E100.

The table below from page 208 states that NVIC_ISER0 register is at memory address of 0xE000E100, which is correct and validated by me in my code.

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Now, from page 210:

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This is the part things start to sound wrong to me: This makes me to think that, "hmm, ISERx registers are the first registers in NVIC block, so, if it is said to have an offset of 0x100, then it means that base address for NVIC register block is 0xE000E100 - 0x100 = 0xE000E000. But at this point, it conflicted with the above information which states(or at least I evaluated as so) that the base address for NVIC is 0xE000E100.

And finally, from page 219:

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Which clearly states that both the base address is 0xE000E100 and NVIC_ISER0 has an offset of 0x100.

So, where am I wrong at?

Best Answer

I believe that offset referred to in Table 4.3.2 is from the bottom of the M4's System Control Space. This is defined as part of the M4's Private Peripheral Bus (as mentioned in your document). It is a 1 MB address space from 0xE000E000 to 0xE00FFFFF. So, when it says Offset 0x100, that is 0xE000E000 + 0x100 as you've found.

You can read more about the M4's memory mapping in the technical reference manual on page 3-39, and in the ARMv7-M architecture reference manual, section B3.

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