In practice, you will never explicitly use one hot encoding. Rather, you should design your VHDL file so that you use enumerations instead of explicit states. This allows the synthesis tools that you use to generate your design to come up with their own preferred encoding. In a CPLD, this would probably be dense coding, because gates are more abundant than flip flops. In an FPGA, this would probably be one hot, because flip flops are more abundant. In other random cases, the synther might think that gray coding, or sequential coding, might be better.
However, to answer your question, how does this perform a rotation? (note I am using your original 3-bit state, even though your question regards 4 bit states)
Consider state = "001". Thus, state(1 downto 0) = "01". Also, state(2) = '0'.
Thus, when you do state <= state(1 downto 0) & state(2), you are doing state <= "01" & '0'. This now means state = "010"; a left rotation by one bit.
In plain language, to rotate an n-bit vector to the left by one bit, take the lower n-1 bits, and concatenate the MSB on the right side of it. In this example, it's taking the state(1 downto 0) bits, and concatenating state(2) on the right side.
In contrast, a right rotation would be represented as state <= state(0) & state(2 downto 1). This takes the LSB, and then concatenates the upper n-1 bits on the right side of it. For state = "001", this right rotation would be like state <= '1' & "00". This now means state = "100".
Your second "FSM" code has many problems, primarily in the last process — process (current_s, input). Just a few examples to start with:
- This is an asynchronous process, so you must list all of the signals used inside of it in the sensitivity list. Failing to do this means that the simulation will not match the behavior of the actual hardware.
- Since not every output is assigned on every possible path through the code, you're creating an enormous number of implicit latches, which will probably simulate OK but give you lots of problems in synthesis.
In addition, this is a poorly-asked question:
- You didn't document the relationship between
Clk and clk_fast.
- You didn't format (e.g., indent) the code to make it easy for others to follow.
- You didn't comment the code so that we could figure out what your intent was.
Anyway, in general, an FSM is not the recommended approach for this sort of problem. What you really need to do is set up a pipeline to do the FIR arithmetic. This would allow you to eliminate the fast clock altogether, along with the complicated FSM logic. The module will produce the same output as the original module, except that it will be delayed by the number of stages in your pipeline.
Best Answer
In VHDL you describe the FSM states with an enumeration type like this:
This type has no meaning on how to represent the enumeration literals (the state names) as binary values in you target device. It can be: * sequential * gray code * johnson code * one-hot code * ...
You can even specify your own user-defined encoding.
The synthesis tool will chose based on: * number of states * number of transitions * transition patterns, e.g. parallel paths in your FSM * need output format * timing requirements * optimization strategy
what will be the best encoding. For example if you enable speed optimization, it might chose one-hot more often, because it's easier to check, and can handle higher frequencies. If you optimize for area, it will decide for more compact codes like gray or sequential (binary numbers).
I have seen one-hot encoded FSM with up to 31 registers (states) in Xilinx synthesis tools.
You can specify a default FSM encoding globally by synthesizer options or per FSM or per enum type with VHDL attributes.
An enumeration type is a discrete type. All enumeration literals have a position number (
T_STATE'pos(ST_ERROR)is 4). Because of that, the tools can handle enumeration literals internally as integers, because a position on the number-scale is an integer value. But this fact does not mean, that each state will be encoded as the binary format of it's position number.