VHDL FSM Moving Average

vhdl

I'm trying to write a VHDL moving average (evenly weighted) module that uses FSMD(ata). From what I understand, the states needed would be something like fetch, divide, output. Below is the process I wrote, but I feel like my logic is a bit off. Note that the data I'm averaging is just a constant array of 8 bit numbers, so I figured it should be fine to use a non-causal design.

The data has 64 entries, and at the moment the window for the average is 4.

process (clk,rst) is

    variable temp : integer range 0 to 1020;
    begin
        if rst = '1' then
            count  <= 0;
            n_state <= s0;
        elsif (clk'event and clk = '1') then
            c_state <= n_state;
            case c_state is
                when s0 =>
                    for i in 0 to (len) loop
                        temp := temp + pattern(count+i);
                    end loop;
                    n_state <= s1;
                when s1 =>
                    temp := temp/4;
                    n_state <= s2;
                when s2 =>
                    data <= std_logic_vector(to_unsigned(pattern(count),8));
                    data_avg <= std_logic_vector(to_unsigned(temp,8));
                    n_state <= s0;
                    count <= count+1;
                end case;
        end if;
    end process;

How wrong does this look?

Best Answer

A few problems I can see right away:

You don't [re-]initialize temp anywhere.
You don't have any limit checks for count (is it a subtype or just a natural/integer? What happens with pattern(count+i) when you approach the limit? How do you roll over?)
Your for-loop is 0 to len - are you sure you didn't mean 0 to (len - 1)?
Since your entire state decode process is clocked, you don't really need n_state at all. Note that you're not even initializing c_state (but you're still decoding it). Either make your state decode a separate combinational process or just get rid of n_state and assign to c_state directly.

Otherwise, it depends on your design goals. If you don't care about throughput but need to run at a very high clock rate, you might want to perform your addition sequentially instead of in parallel, for example.

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Finite state machine FSM model of FIR filter in VHDL for FPGA

Your second "FSM" code has many problems, primarily in the last process — process (current_s, input). Just a few examples to start with:

This is an asynchronous process, so you must list all of the signals used inside of it in the sensitivity list. Failing to do this means that the simulation will not match the behavior of the actual hardware.
Since not every output is assigned on every possible path through the code, you're creating an enormous number of implicit latches, which will probably simulate OK but give you lots of problems in synthesis.

In addition, this is a poorly-asked question:

You didn't document the relationship between Clk and clk_fast.
You didn't format (e.g., indent) the code to make it easy for others to follow.
You didn't comment the code so that we could figure out what your intent was.

Anyway, in general, an FSM is not the recommended approach for this sort of problem. What you really need to do is set up a pipeline to do the FIR arithmetic. This would allow you to eliminate the fast clock altogether, along with the complicated FSM logic. The module will produce the same output as the original module, except that it will be delayed by the number of stages in your pipeline.

Electronic – State switches in FSM

What you can do is create an idle state, and when you detect a button press you switch straight to the idle. Then you can have a counter in idle which waits for a while before you start scanning buttons again.

For example:

-- include numeric std
signal idle_counter : unsigned(31 downto 0);

      ...

      when state3 => 
        case bcd_val is
          when "01" => 
                Send <= '1';
                scannel_val <= "0101"; 
                fsm_state <= idle;   -- switch to idle
          when "10" => 
                Send <= '1';
                scannel_val <= "0110";
                fsm_state <= idle;   -- switch to idle
          when others => 
                scannel_val <= "0000";
                Send <= '0'; 
                fsm_state <= state1;   -- carry on scanning
        end case;
        idle_counter <= (others => '0');
        ...
      when idle =>
        if (idle_counter < some_timeout) then  -- some_timeout is how long you want to wait (in clock cycles)
           idle_counter <= idle_counter + "1"; -- increment counter
           fsm_state <= idle;                  -- stay here
        else
           idle_counter <= (others => '0');    -- reset counter
           fsm_state <= state1;                -- go back into checking
        end
        --scannel_val is valid here, so you can do something with it if you'd like.
        ...
      when others => scannel_val <= "0000";

There is one process in this code you've posted.

It starts with

scan_fsm : process (reset, clk) <= Sensitivity list
begin  -- process key_scanner

and ends with

end process scan_fsm;

The clock and reset are part of the sensitivity list. That means that this code is only going to be triggered when either clock changes or reset changes.

De-bouncing can be done in a separate process. Basically, you want to make sure that the button was pressed for a number of microseconds before it triggers. What we want to do is save the value of the input for a number of clock cycles. Then only register a 1 when the history has been constantly 1 for for the past 32 clock cycles.

Example:

-- these are our row inputs (to become bdc_val)
signal row1 : in std_logic; 
signal row2 : in std_logic;

...
-- this is our history vector
signal row1_z : std_logic_vector(31 downto 0);
signal row2_z : std_logic_vector(31 downto 0);

-- debounced signal
signal bcd_val : std_logic_vector(1 downto 0);

-- a whole vector of ones for convenience
signal ones    : std_logic_vector(31 downto 0);
...

ones <= (others => '1');

-- generate our histories
gen_z : process (reset, clk)
begin  
  if (reset = '1') then
    row1_z <= (others => '0');
    row2_z <= (others => '0');
    bcd_val <= (others => '0');
  elsif (rising_edge(clk)) then
    row1_z(31 downto 1) <= row1_z(30 downto 0); -- shift everything up 1
    row1_z(0) <= row1;                          -- save the most recent input
    row2_z(31 downto 1) <= row2_z(30 downto 0); -- shift everything up 1
    row2_z(0) <= row2;                          -- save the most recent input

    -- we only want bcd_val to be 1 when the entire row history for the past 32 cc is 1
    if (row1_z = ones) then
      bcd_val(0) <= '1';
    else 
      bcd_val(0) <= '0';
    end

    if (row2_z = ones) then
      bcd_val(1) <= '1';
    else 
      bcd_val(1) <= '0';
    end
  end
end

Best Answer

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