Electronic – Op-amp and amplifying the voltage in negative range

Audio inputs are usually capacitively coupled. This means low frequencies are attenuated and DC, the lowest frequency of all, is blocked entirely. Usually audio circuits are designed such that low means something around the lower limit of human hearing, about 20 Hz.

A typical audio input stage might look like this:

^{simulate this circuit – Schematic created using CircuitLab}

C1 serves to block any DC. The parallel combination of R1 and R2 set the input impedance. You can also view this arrangement as a simple low-pass RC filter, with the RC time constant, and thus the cutoff frequency of the filter, defined by R1||R2 and C1.

R1 and R2 meanwhile create a voltage divider that set the DC level as seen by the ADC or whatever follows. Usually R1 and R2 will be equal so that the DC level is midway between the supply rails, to allow for maximum voltage swing in either direction.

1. Why is there 10k resistor at DAC output? Is it used as current limiter? Why is current limiter needed if op-amp sinks very little current at its input?
2. Why is there a capacitor at the same + input?

The 10k and 470p combination form a low-pass filter. Cut-off frequency is given by \$ f = \frac {1}{2 \pi R C} = \frac {1}{2 \pi 10k \cdot 470p} = 34~kHz \$. It will reduce any high frequency switching noise from the DAC.

3. At the feedback resistor(453k one), why is there a capacitor across it?

This reduces the gain of the amplifier at high frequencies. Again this helps eliminate switching noise and amplifier stability.

4. Why is there extra connection from from DAC REF voltage(2.5V) to the voltage divider of negative voltage feedback of op-amp?

We can see that the DAC is powered from +3 V and GND. This is therefore the maximum and minimum possible output voltages. (It will actually only give up to 2.5 V on the output as that is the Vref setting.) The amplifier, however, is powered from +70 V and -70 V which implies that we are expecting to drive it positive and negative with respect to ground.

Since the DAC can only give a positive output we can assume that 1.25 V (half of Vref) represents the mid-point or "zero" of the AC signal output. We therefore reference the amplifier to that point.

Removing the offset

We have one little problem left: we want 0 V out of the amplifier when ADC out is 1.25 V. To do this we need to raise the inverting input reference point by \$ \frac {1.25}{A} \$ where A is the gain. This is done by tweaking the ratio slightly with the potential divider ratio of 16k2 and 16k9. (These add to 33k3 which makes me think the values were worked out for convenience on a 3.33 V reference.) In any case it's 51.06% of 2.5 V. The amplifier will have to drive the output to less than 1.25 V to pull the inverting input down to match the non-inverting input. If the calculation has been done correctly the balance will occur when the output is at 0 V.

I'll leave it as an exercise to the reader to confirm the values are correct!