Electronic – Parallel RAM without large number of pins

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Back in the 1970s, Texas Instruments had a now-discontinued range of products that they called GRAM (and read only equivalent GROM) which was basically a standard memory chip with address and data all multiplexed onto 8 pins. You'd start an operation by sending the chip two bytes of address and then every time you pulsed either the read or write pin it would read or write a byte using the bus, then increment the internal address counter. The result was a memory chip that was almost as fast (at least for sequential access operations) as a standard parallel memory chip, but which only need a 16-pin package, rather than the 28-pin packages other similar memories of the day needed.

Today, for similar applications, you'd probably most often use SPI-accessed serial memory — but the problem is that such memories are quite slow (most have a maximum throughput of about 20Mbit/s; some run as fast as twice that, but I haven't found any faster than that) whereas a modern equivalent of those TI parts could be much faster than that, easily allowing 100+Mbit/s access.

Does anything exist that's still in production and which behaves similarly to those TI chips? The closest I can find today are custom-purpose parts, e.g. the VLSI VS23S010D, which combines a memory device that supports the kind of interface I'm looking for along with a display driver, which puts the pin count up to 48 pins… I'm ideally looking for something in a 14 or 16 pin package (I think 14 is the realistic minimum – 2x power, 8x data, clock, address select, read byte, write byte).

Best Answer

The appropriate standard solution is probably QSPI (also called QPI, or also SQI). It is somewhat an extension of the SPI interface, but uses four (quad, hence the Q in the acronym) data bits (IO0/IO1/IO2/IO3) instead of a single signal for each direction (MISO/MOSI).

So the chips are very small (typically SO-8), and the interface is very efficient: you need to send the address for each read or write command, but then you can read multiple bytes in burst, four bit at each clock cycle. Max clock speed is typically ~104MHz for flash. It can be made even faster using a Dual Data Rate signaling (four bits at each clock edge, both rising and falling: so eight bits at each clock cycle - typically, flash chips will max out at 80MHz in this mode).

The chip datasheets will provide all details about the exact meaning/usage of each signal. To illustrate, here is a read command timing diagram (in single data rate mode, and taken from this datasheet):

Here, you see you need 14 clock cycles to get the first byte (at 80MHz, it means 175ns access time). But if you need more bytes, just add 2 cycles per byte (25ns). So reading in burst will make it much faster than a typical 70ns or even a 45ns flash parallel chip.

You can easily find NOR flash parts from a lot of manufacturers, using this interface. Note that their performances (max speed, dummy cycles count) and features (Quad i/O or just Dual I/O, DDR support) will vary, so check the datasheet.

RAM is a bit more difficult to find, but still available, notably from Microchip (e.g. 23LC512), ON semi (e.g. N01S818HA) and ISSI (e.g. IS62WVS2568GBLL-45). They are slower than flash, though. But the ISSI I suggest above still goes up to 45MHz (single data rate) with apparently a minimum read cycle needing 11 clocks for the first byte. Or put in another way: 200ns + 45ns per byte (180Mbit/s throughput), which is not bad, and exceeds the GRAM speed you indicated.

Also, note that a lot of high-end MCUs (from NXP, ST, ...) support this interface in hardware.

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Electronic – RAM device / timings for small VGA project

Here's how I'd do it...

I would start with a Xilinx Spartan-6 FPGA. The reason I'd go with this is because they have "hard cores" for a DDR-SDRAM interface. By hard core, I mean that the circuitry for this memory interface is a dedicated chunk of logic and not in the normal "user programmed fabric of logic". This means that you're going to meet timing, and you don't have to write this logic on your own.

Next, I'd hook up some DDR2 SDRAM to the part. DDR2 SDRAM is fairly inexpensive, easy to get, and certainly fast and large enough for what you want to do. I'd start with a 16-bit wide data bus, and increase that if you need more speed. You can use the Xilinx CoreGen or Memory Interface Generator to get your DDR2 interface core.

The rest is "relatively easy", in that it's just moving data around and generating the proper sync pulses.

One major down-side to this approach is that you're basically limited to using BGA's for both the memory and FPGA. One plus side is that there are FPGA development boards that already have this circuitry on it.

Electronic – wrong with this attempt at an SDR RAM in Verilog

I got this working, with one specific change although to be honest some other edits may have helped too.

I thought about how drive_data is set up using combinatorial logic, but the outdata register is clocked. Confirmed with behavioural sim, this means that stale data is driven out during the first part of a read cycle, before the address is latched.

I "fixed" this by changing the always block that sets outdata to do so on every clock, meaning the right data gets in there during the setup phase while address is valid on the bus, before the OE strobe comes along.

I also refactored my memory bus handling into a submodule (inverting the control signals).

module emif(
    input clk,
    input [1:0] addr,
    inout [15:0] data,
    input ce,           // note these signals are active high
    input we,           // (opposite to the PCB signals)
    input oe
    );

wire drive_data;
reg [15:0] mem [0:3];
reg [15:0] em_outdata;

assign drive_data = ce && oe && !we;
assign data = drive_data ? em_outdata : 16'bz;

// writes data to small mem
always @ (posedge clk)
begin
    if (ce && we) begin
        mem[addr] <= data;
    end
end

// reads data from small mem
always @ (posedge clk)
begin
    em_outdata <= mem[addr];
end

endmodule

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Electronic – RAM device / timings for small VGA project

Electronic – wrong with this attempt at an SDR RAM in Verilog

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