If you want affordable boards, forget about blind vias, via in pad, and filled vias. This is a good presentation on BGA routing, albeit for very high-density boards, but the basic principles will be the same for less demanding layouts.
SMD pads vs NSMD pads is something you need to ask the company doing your BGA assembly about. The latter seems to be preferred. Some chip manufacturers have recommendations, as well.
If you have questions, this forum is very useful. You can also learn a lot by reading the various posts.
1) Crystals should not be routed this way. Traces should be shorter and as symmetrical as possible. You should connect capacitors to GND in a single point, so that you are not picking any noise from the ground plate. This is especially important for RTC crystal. With current routing you might get problems with generation start/failure if you are unlucky.
2) Checkout my single-layer board for ARM : http://hackaday.com/2011/08/03/an-arm-dev-board-you-can-make-at-home/ - even this nightmare works (only 1 decoupling cap). Defenitely what you have here will work. You may add some extra caps (like some 25uF electrolytic + 2.2uF ceramic) on the backside of the board, you have plenty of space there, and both VCC & GND together. The only thing I don't like is thin traces to your caps. They should be as wide as possible. In my design, the only capacitor was connected by like 2mm-wide traces.
Also, look at C5: You can move it to the right a little, move via closer to the cap and connect it with short wide track. When you via is under the chip, you cannot have wide tracks. Same for C6 and C7.
Also, if you are going to manufacture this at home,you'll have problems making vias under QFP chips.
3) Ground plate is more than enough. There is no much need to have solid ground plane except a square under chip where all decoupling caps are connected, it won't help with ground noise much. Ground plate is needed for controlled impedance, which is not important in your case. But your GND connection to contacts should be as wide as possible. This is general rule: VCC & GND nets should have wide tracks.
4) Yes, this is perfectly ok for low-speed ARMs.
In my case I even had no back side, and it was still working ;-) The only thing to improve if you are manufacturing on a factory is to have a small VCC square on the bottom layer in the middle of the chip, and connect it to the top using some 4-9 vias instead of 1. For VCC & GND planes you always need to have as low as possible resistances and inductance so that caps can easier filter noise => you need wider and shorter tracks and more parallel vias. But in this specific design it is not a requirement.
So, it will work even now without modifications. After mentioned changes it will be perfect.
Best Answer
Good layout requries proper planning of the power distribution first.
To achieve this, you should plan the layout such that components that form a logical group are placed near each other; from this, separation of functions becomes much easier to achieve.
If you are in a mixed signal environment with sensitive analogue signals, then there is an excellent article on planning the planes.
If you are using glue logic that is fairly recent, it will have fast rise and fall times which will definitely couple energy to nearby planes and tracks.
If you are using ADCs for data acquisition, then there is another excellent article on the subject.
On that note, ADC manufacturers have helpfully grouped all the analogue signals together so that effective noise isolation may be achieved. See the device below for an example:
I also went into some detail on this subject at this previous answer.
Good layout does not have a one size fits all, but there are accepted best practices.