The explanation of a PLL is here, for a PLL, what is the meaning of the following terms?
- Capture Range ?
- Lock Range ?
What is it about the PLL circuit that might have these two terms span a different range. Or are they always the same?
Electronic – (phase lock loop)PLL?, Lock Range & Capture Range
pllterminology
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Can you post more details regarding the target frequency, jitter and loop bandwidth (required settling time)? Also, what kind of oscillator do you want to use (external with a DAC, with/without dithering?, an on chip digital counter/accumulator)?
If you're happy with a digital "oscillator" (i.e. an overflowing accumulator) and its jitter then the rest of the circuit can be fairly simple:
- a counter (PFD) counting number of cycles between the reference and the (optionally divided) PLL output,
- a digital filter - anything will do assuming it does the integration (an accumulator) and it has a zero (minus (or plus?) a scaled PFD output) to stabilize the loop, optionally one or more poles above the loop bandwidth to reduce the control value "ripple" at reference frequency (only matters if fref
- most significant bits of the digital filter output (DVCO control value) are given as an input to the overflowing accumulator (DVCO).
As for the loop bandwidth, if not enforced by settling time, decide it based on the noise contributions of all components.
- If the jitter comes mainly from the reference or from PFD - use a smaller bandwidth,
- If the noise comes from the oscillator - increase it.
In case if the reference signal is phase or frequency modulated - use a loop bandwidth lower than the smallest frequency of the signal modulating the reference.
Trickier techniques are used if the output frequency is close or equal to clock frequency and/or if the low jitter or very fast locking range is required. Maybe in your case they are not needed, besides they may not be well suited to an FPGA implementation.
If input frequency and feedback frequency (after dividing) are the same then the PLL is potentially going to fall into a state of in-lock because the phase detector doesn't care about phase differences that are multiples of 2\$\pi\$: -
As the "wandering" clock leaves perfect phase alignment with the static clock (left side), the EXOR output starts to produce thin pulses that become wider as the the wandering clock leads the static clock by greater amounts. At perfect anti-phase between the two clocks the EXOR output is a constant "1" and as the leading extends even more, the EXOR output repeats itself as the phase difference between wandering clock and static clock is 2\$\pi\$ (right side).
Best Answer
There is much out there on the basic descripton of a phase-locked loop (PLL). Basically, a PLL is a phase comparator producing a feedback signal to adjust a independent oscillator to exactly match the frequency of some incoming signal. The output of the oscillator then is a locally produced copy of the incoming signal. That by itself may not sound useful, but here are some things that can be done with this:
Capture range and lock range refer to how close the local oscillator frequency needs to be to lock onto the incoming signal. Since the phase comparator goes thru its full output range over only 1 cycle of mismatch between the incoming signal and the local oscillator, it's output becomes effectively gibberish when the frequency difference is high. It goes back and forth so fast that the local oscillator doesn't have enough time to adjust.
The capture range is the incoming signal frequency range over which the phase comparator and oscillator can react fast enough so that phase lock is achieved before the phase comparator goes thru another cycle. This is basically what the input frequency needs to be for a cold start.
Tracking range is the range of input frequencies over which the oscillator can stay in lock once lock was achieved. This is a wider range than the capture range since the comparator is already in lock, so incoming frequency variations are dealt with incrementally.