Electronic – PIC16f84A Unable to delay properly

This sort of delay scales inverse-linearly with clock speed as long as there are no interrupts or similar running (ie double clock speed and delay halves).

• If a delay takes 1 mS at Z Mhz it will take Y/Z mS at Y Mhz.

• If you need a count of X loops to delay eg 1 mS at Z MHz
  then you will need X * Y/Z loops at Y MHz.

This is useful: PIC delay routines.

To work out how many loops are needed you 1st need to know the number of clock cycles or uS per instruction at the clock speed used.

For the PIC that you have shown, most instructions take one "unit" of time.
This will vary among processor families.
Some take 4 crystal clock cycles per instruction, some take 1, some take more.
Assume you know Tw = basic instruction unity time at W Mhz.

In a PIC most instructions execute in Tw at W Mhz where Tw is usually 4/F_Mhz in the older style 14 bit core PICs. .
BUT check this for the processor you are using.

In a PIC the decfsz skip instruction takes one time unit if the test fails (register is non zero) and two time units if the test passes - register is zero and skip occurs.
Some processors may take one unit if test fails or passes or two whether it fails or passes or ... - check what applies for the processor you are using.

So here the main timing loop is 3 time units usually and 4 units only when the register reaches zero.

Work out the basic unit time (say for nop instruction) at clock speed W Mhz and one mS then needs a count of x in 'movlw x' of

• count = 1000 / Tw / 3

  where Tw is time for a nop instruction and the 3 is due to 3 x single Tw length instructions in the loop.

If a NOP took 0.5 uS then

• Count = 1000/0.5/4 = 500.

As an 8 bit counter can only count to 255, if variable_temp is 8 bit then this count is too large and a double byte counter is needed.

Something more like below. Here you have inner and outer loops. Each inner loop runs for K_Count_Low loops and the inner loop is called K_Count_High times. Counters are 8 bit so should be set to <= 255.
Maximum delay is ~~~= 255 x 255 x 3 x Tw.
Outer loop handling , included nops etc change this. Seeing exactly how is part of learning how this all works.

    movlw   K_count_High  
    movwf   Counter_High  

LoopOuter:

     movlw   K_count_Low
     movwf   Counter_Low

LoopInner:

     nop   
     decfsz  CounterLow, 1   
     goto    LoopInner  

     decfsz  CounterHigh, 1   
     goto    LoopOuter  

     Call "We are the Borg of Pentium. Division is futile! We will approximate you"  

E&OE.

This is not a good circuit for a variety of reasons. There are a lot of crappy circuits on the internet. In fact, the fraction of crappy circuits is higher on the internet than in real life. Those that know what they are doing and design a circuit to a particular requirement don't consider it a big enough deal to publish and often can't due to confidentiality issues anyway. It's the wannabes that can barely spell NPN that spend a week getting their LED to blink that then proudly want to show off their herculian accomplishement to the world.

Just a few problem off the to of my head:

1. Is Q2 rated for 10 V reverse bias accross its B-E junction? That is certainly possible, but many small transistors aren't rated for that.

2. Your passive pullup that drives Vpp will drop some voltage. It seems neither you nor whoever designed this circuit even looked at the programming spec. See the spec for Ihh in Table 5-1 AC/DC CHARACTERISTICS, section 5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS on page 13. Multiply that current times R4, then subtract that voltage from your 13 V supply. Your Vpp voltage is now out of spec.

3. On the same table, notice the maximum Vpp rise time. Do you really think a 10 kΩ passive pullup can meet that? Maybe it can, but maybe not. Again, I don't like the passive pullup to drive Vpp high.