Electronic – pic18f2420 pwm frequency

First: Do you have a 20 MHz crystal or crystal oscillator? Those are two different things. A crystal oscillator will all on its own generate a 20 MHz clock signal for the PIC and you use the external oscillator option with it.

On the other hand, the quartz crystal is an external part of the internal oscillator and internal components together with the crystal and load capacitors make a complete oscillator. In such configuration, you use various crystal modes. Also take a look at figure 2.2 on page 27 of the datasheet.

Now to set up this part correctly, you need to understand a few things, so I'll quote the datasheet:

When the PIC18F4550 is used for USB connectivity, it must have either a 6 MHz or 48 MHz clock for USB operation, depending on whether Low-Speed or Full-Speed mode is being used.

You need to combine things so that the USB clock is 48 MHz or 6 MHz and then you need to set-up the microcontroller operating frequency so that it works at suitable speed. Those two clocks may be different.

On page 26 of the datasheet, you have a nice diagram which you should take time to analyze. The USB PLL input expects 4 MHz frequency which it will use to generate the 96 MHz from which it will derive the operating frequency for USB and the microcontroller.

In your screenshot, the 20 MHz are divided by 5 to get the 4 MHz needed for USB PLL which then raises that to 96 MHz, as seen in the PLL prescaler section.

Then you have the system clock postscaler section. It is currently set to use the 96 MHz created by USB PLL and divided by 2 as the main system clock. You also have other options to set the main systme clock. I can't remember exactly what they are and I've just formatted my HDD, so mikroC isn't installed yet. They should offer you to derive the system clock from an internal oscillator or directly from the clock used to generate the 4 MHz for the USB PLL or as it is shown in the screenshot from the 96 MHz generated by the USB PLL.

The point here is that you can independently select the main clock and the USB clock. For example, if you have a 20 MHz oscillator, you could run the PIC main clock at those 20 MHz and at the same time run the USB clock at needed 48 MHz.

Next you have the oscillator selection part. For real crystal oscillators, you should use EC options and connect the output of the oscillator to the OSC1/CKLI pin (in your case pin 9). You can then use the 20 MHz oscillator to drive the PIC.

In case you're using a crystal, you need to use the crystal options. They are XT, for low frequency crystals, up to 4 MHz, and HS for high frequency crystals up to 20 MHz, if I remember correctly.

As for which crystal is better, well that depends on a lot of things such as which exact crystal you're using, its characteristics, characteristics of the PLL used in the PIC and so on.

Usually low frequency crystals drift less over time and produce cleaner signal while high frequency crystals often give as their output a harmonic of some lower frequency and the signal is usually weaker. I myself would use the 4 MHz crystal here.

Also I forgot the last part of your question: In the "Oscillator frequency" field, you should enter the effective operating frequency of the PIC, that is to say the frequency the "primary clock" on figure 2.1 on page 25 of the datasheet sees. In your particular case, that would be 48 MHz.

So to sum this up: In the 20 MHz crystal case, you should first set the "oscillator selection" to HSPLL. That will give 20 MHz at the input of "primary oscillator" in the above-mentioned figure 2.1. Next, you should set the PLL prescaler to divide by 5, so you get 4 MHz which are multiplied by 24 to get the 96 MHz for USB. Next set the "USB clock selection" to 96 MHz divided by 2 and set the "System clock postscaler selection" to 96 divided by two. Finally, set the Oscillator frequency to 48 MHz and you're done with this part.

For the 4 MHz crystal, you should first set HSPLL. Set the PLL prescaler to divide by 1 and then set the "USB clock selection" to 96 MHz divided by 2 and set the "System clock postscaler selection" to 96 divided by two and set the Oscillator frequency to 48 MHz and that's it.

You should upgrade to MPLAB-X. In there is a handy configuration bits setting window. Using that I have come up with the following settings:

// PIC18F4550 Configuration Bit Settings

// 'C' source line config statements

#include <xc.h>

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

// CONFIG1L
#pragma config PLLDIV = 5       // PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)

// CONFIG1H
#pragma config FOSC = HSPLL_HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = OFF        // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)
#pragma config VREGEN = OFF     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

That should use the PLL to divide the 20MHz crystal by 5 to make the needed 4MHz into the PLL, then the system clock is taken from the output of the PLL (96MHz) divided by 2, giving 48MHz. You're good to go with USB too if you want, by turning on the USB regulator.

Without knowing what your crystal is I can't be sure, but you might want to increase the load capacitance to 33pF instead of 22pF.