# Electronic – Power consumed by a CPU

capacitorcmoscpumosfetpower

I think the power for a CPU with current I and voltage U is I · U.

I wonder how the following conclusion from Wikipedia is derived?

The power consumed by a CPU, is approximately proportional to CPU
frequency, and to the square of the CPU voltage:

P = CV2 f

(where C is capacitance, f is frequency and V is voltage).

MSalters answer is 80% correct. The estimate comes from the average power necessary to charge and discharge a capacitor at constant voltage, through a resistor. This is because a CPU, as well as every integrated circuit, is a big ensemble of switches, each one driving another one.

Basically you can model a stage as a MOS inverter (it can be more complicate, but the power remains the same) charging the input gate capacitance of the following one. So it all comes down to a resistor charging a capacitor, and another one discharging it (not at the same time of course :)).

The formulas that I'm going to show are taken from Digital Integrated Circuits - A design perspective from Rabaey, Chakandrasan, Nikolic.

Consider a capacitor charged by a MOS: the energy taken from the supply will be

$$E_{VDD} = \int_0^\infty i_{VDD}(t)V_{DD}dt=V_{DD}\int_0^\infty C_L \frac{dv_{out}}{dt}dt = C_L V_{DD} \int_0^{VDD} dv_{out} = C_L {V_{DD}}^2$$

While the energy stored in the capacitor at the end will be

$$E_{C} = \int_0^\infty i_{VDD}(t)v_{out}dt = ... = \frac{C_L {V_{DD}}^2}{2}$$

Of course, we don't wait an infinite time to charge and discharge the capacitor, as Steven points out. But it's not even dependent on the resistor, because its influence is on the final voltage of the capacitor. But that aside, we want a certain voltage un the following gate before considering the transient over. So let's say that it's 95% Vdd, and we can factor it out.

So, independently on the output resistance of the MOS, it takes half of the energy that you store in the capacitor to charge it at constant voltage. The energy stored in the capacitor will be dissipated on the pMOS in the discharge phase.

If you consider that in a switching cycle there are a L->H and a H->L transition, and define \$f_S\$ the frequency at which this inverter completes a cycle, you have that the power dissipation of this simple gate is:

$$P = \frac{E_{VDD}}{t} = E_{VDD} \cdot f_S = C_L {V_{DD}}^2 f_S$$

Note that if you have N gates, it's sufficient to multiply the power by N. Now, for a complex circuit the situation is slightly more complicated, as not all the gates will commute at the same frequency. You can define a parameter \$\alpha<1\$ as the average fraction of gates that commute at every cycle.

So the formula becomes

$$P_{TOT} = \alpha N C_L {V_{DD}}^2 f_S$$

Small demonstration of the reason because R factors out: as Steven writes, the energy in the capacitor will be:

$$E_C = \dfrac{V_{DD}^2 \cdot C}{2} \left(1 - e^{\dfrac{-2T_{charge}}{RC}}\right)$$

so apparently, R is a factor of the energy stored in the capacitor, due to the finite charging time. But if we say that a gate must be charged to 90% Vdd in order to complete a transition, than we have a fixed ratio between Tcharge and RC, which is:

$$T_{charge} = \frac{-log(0.1)RC}{2} = kRC$$

one chosen it, we have again an energy which is independent of R.

Note that the same is obtained integrating from 0 to kRC instead of infinite, but the calculations become slightly more complicated.