The MSP430G2452 has three Timer A bugs in both revisions, any of which might be affecting you. They can be read in the Errata for the chip. I believe maybe Bug TA12:
Interrupt is lost (slow ACLK):
Timer_A counter is running with slow clock (external TACLK or ACLK)compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK the CCRx register increment (CCRx = CCRx+1) happens before the Timer_A counter has incremented again. Therefore the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt gets lost.
Workaround: Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterwards.
Even if this is not the case, you can easily fix this. You are using the default 1MHz Master clock. You can change this to 2 MHz or 4 MHz with a simple code change, at which point the same divider would produce a VLO of 24KHz or 48Khz. This would allow you to set a timer count a bit higher, again either 12 or 24, avoiding the lower count issue. Of course, testing is needed to be sure.
Your alternative plan also works. If you are not too concerned with low power, simple delays would work. Of course, as this is running on the Master clock of 1Mhz instead, you will need to calculate an apropos delay, and realize that there will be some slight drift.
First thing you need to recognize is that designing with a 16-bit ADC is not trivial. Even at 1 sample/s, you need to pay extreme attention to every aspect of the design to achieve 16-bit precision, or even more difficultly, 16-bit accuracy. At 130 MSa/s, everything is even more difficult.
The parts you need to do this kind of design simply won't be inexpensive. First, because of the extreme precision and careful testing needed to achieve the required performance. Second, because this kind of thing isn't done in mass-market products, so the parts aren't built in the kind of extremely high volumes that can bring the price down for everyone.
As Dave says in another answer, be sure you really need 16 bits before you go down this road. But maybe you really need 12-bit precision, and you know that if you use even a 14-bit ADC you're going to have a hard time achieving that, so you're designing with 16-bit ADC and optimize everything else as much as you can.
Another key is likely to be understanding exactly what specs you need to make your system work, and don't over-specify your clock jitter. In an SDR application, you're going to be doing math on the samples to extract specific frequency bands, etc, which will have an averaging effect over many cycles. So you might not care too much that absolutely every sample is timed perfectly, only that over your calculation interval, there isn't too much deviation from ideal timing. How much is too much, of course, depends on what kind of math you're doing and how small a signal you need to extract from how much noise.
CTS Valpey, for example, has XO's with rms jitter specs as low as 200 fs. But this spec is defined when the phase noise is integrated over a specific frequency band, 12 kHz to 20 MHz (relative to the carrier). If the total cycle-to-cycle jitter is considered, the spec jumps to 3-6 ps, depending on the center frequency.
Let me also address one comment you made in your question:
OCXO are extremely stable over time ( years ) and are usually used for that.
The "ovenized" part of that product mainly reduces the drift due to temperature change in the surrounding environment, which can be significant over time scales of minutes or seconds, not just years. It will also reduce wear on the part due to thermal cycling and improve the stability on a time scale of years.
For the < 100 fs jitter range you're looking for, you might actually need an OCXO to prevent small temperature changes affecting the performance during the time it takes to measure the jitter accurately enough to know you've achieved your spec.
Best Answer
What you are trying to do is very challenging. Frequency measurement boils down to measuring the time T between corresponding points on the signal waveform (e.g., rising zero crossings) over some number of periods N. The period of the waveform is T/N, and equivalently, the frequency is N/T.
Simple frequency counters just count the number of times that the signal crosses a fixed voltage threshold over a fixed amount of time, and the resulting measurement is relatively crude, with a potential error in N of ±1 whole cycle. This, combined with the accuracy of the counter's internal timebase, determines the accuracy of any particular measurement.
What you are proposing by using an ADC is much more sophisticated, but there are still many issues to overcome before you get to the level of accuracy you're proposing. You'll know N exactly, so the accuracy depends entirely on your ability to measure T. See the following diagram.
To start with, the samples you take are not going to be synchronized to the signal waveform, so it will be necessary to interpolate the position of the actual zero-crossing from the samples on either side of it. The problem is that each sample, represented by a "fuzzy" ellipse above, has a significant amount of uncertainty associated with it.
There are voltage errors, caused by:
There are also timing errors, caused by:
This means that your estimate of the actual waveform (shown as the heavy black lines) could be anywhere in the "error band" represented by the dashed lines. In other words, the interpolated position of each zero crossing will have a timing uncertainty associated with it, shown as ΔT. Note that voltage errors contribute to ΔT because of the finite slope of the signal at each zero-crossing.
The overall period that you're measuring could be as small as T – ΔT or as large as T + ΔT, for a total error of 2ΔT. This means that if you want 12 digits of accuracy, 2ΔT must be less than T × 10-12. Assuming you're taking measurements "quickly" (i.e., T is on the order of 1 second), this means that ΔT must be less than 0.5 ps. 15-digit accuracy would require ΔT less than 0.5 fs. These are not easy numbers to achieve.