Electronic – Problem using FSL with microblaze

fpgamicroblazexilinx

I want to pass some data from my verilog to my microblaze core in ISE 14.7. I was doing some research and it seemed like the FSL was the easiest way to go about this.

What I did was create a peripheral with one 32b input and one 32b output of the FSL variety. I then clicked configure coprocessor and added my new fsl_link to it.

That done, it added fsl_link_0_to_microblaze_0, microblaze_0_to_fsl_link_0, and fsl_link_0 to my Bus Interface window.

I then did a DRC check and I get

ERROR:EDK:3900 - issued from TCL procedure "::hw_fsl_v20_v2_11_f::check_syslevel_settings" line 14
fsl_link_0_to_microblaze_0 (fsl_v20) - FSL_Clk is unconnected. 

ERROR:EDK:3900 - issued from TCL procedure "::hw_fsl_v20_v2_11_f::check_syslevel_settings" line 14 
microblaze_0_to_fsl_link_0 (fsl_v20) - FSL_Clk is unconnected.

All I want to do is pass some register values from my verilog to my uBlaze (doesn't even need to go the other direction for now). What am I doing wrong? I am not sure how I need to set up the clocks by my FPGA runs at 200MHz and my uBlaze is clocking at 100MHz if that helps.

Best Answer

Close the EDK and take a look at the system.mhs file. You should see the FSL clock and reset lines connected to sys_clk. If not, you can add them straight into that system.mhs file and re-generate the bitstream.

You need two lines like this in the BEGIN/END block

BEGIN fsl_v20

  PARAMETER .... 
  PARAMETER ....

  PORT SYS_Rst = sys_rst
  PORT FSL_Clk = sys_clk

END

For a late night read, browse the FSL patent. It won't help you with your implementation, but I find it's always interesting to read up on a technology patent:

http://www.google.com/patents/US7380106

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