Electronic – Proper ways to disconnect ICs during low power states to avoid parasitic/backfeed supply


I’m working on a low-power battery-based AVR-based project that integrates a few different devices including a neopixel strip and an Adafruit pixie. When the overall device is quiescent, I’d like it to draw less than 0.1mA to maximize the LiPo battery life.

I got this all working (measured 0.035mA) but I’m not sure I necessarily did it in the “right” way and I plan to build a product based on this so would like to do it right.

enter image description here
(Not shown: a flyback diode for the relay)

The core concern I have is the “parasitic” powering of devices when VCC is disconnected via current flowing from data pins. For instance, the Pixie (which communicates via serial), has no power down mode and even when “off” drains about a milliamp. So I placed a small relay to disconnect its VCC, and discovered that the serial pin was actually still powering the pixie. Hints elsewhere suggested that many chips have a diode shunting their digital input pins to VCC as power protection. To solve this, I’ve had to suspend the serial library and actually digitalWrite( PIN, LOW ) during sleep.

Same thing with the WS2812b strip — disconnecting VCC still allows the device to be powered from the data pin. And in other designs when I’ve disconnected GND with an N-Channel MOSFET, I’ve seen the reverse – a back flow of current through the data line to ground! (This had to be solved with a diode per a post on PJRC.) The WS2812b’s actually take about a milliamp each even when unlit,

So the question: Is there a general, “clean” way to disconnect VCC and GND from parts of a project during system sleep when there are data pins in the mix. What is the best practice?

Some ideas:

  1. Force VCC to GND (not sure how? Hbridge?). (If I do that, what happens to the data pins that are high?)
  2. Place a tri-state buffer between all data pins and these devices, and during sleep put the tri-state buffer in a high impedance state, disconnect VCC or GND only with P or N mosfet
  3. Disconnect GND only with N mosfet, and place diodes on all data pins
  4. Is there some kind of power latch that disconnects both VCC and GND and puts them into a “high impedance” state (like a tri-state buffer for power?) That way current has no way to flow "out" from the data lines.

Can someone enlighten me to the cleanest, most repeatable way of handling this sort of “load disconnect” problem? (Needless to say, I have spent hours googling this problem with little luck, although I did find this tech note on load switching but it doesn't address back-feed and parasitic power)

Best Answer

When I do this, I usually use CMOS analog switches on the affected data lines.

Something like the ADG812 has 4 channels of SPST switches that are easily suitable for quite fast logic, and provide a really high impedance between the switch nodes when in the off state.

ADG812 off leakage

The nice thing about this is that the technique works for both unidirectional and bidirectional data lines.

These parts also run on a bright smile:

ADG812 power requirements

The usual sequence for power down:

  1. Turn off data path switches

  2. Power down domain.

Power up is the opposite, of course.


These are indeed known by other names, such as pass gates and transmission gates.

These are significantly different from a true tri-state buffer (as you can see in the diagrame in the link above), but for ordinary logic, the effect is better (this is inherently a bidirectional device) but with lower power.