I'm extremely new to VHDL and trying to make some easy projects such that I learn the basics and syntax. I use Quartus 2 at home and ISE 10.1 at the school computer. I wrote exactly the same code in both of them where the code is:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity freq_divider is port(
clk: in std_logic;
clkdividedby2,clkdividedby4,clkdividedby8: out std_logic
);
end freq_divider;
architecture karakter of freq_divider is
signal count4 : std_logic := '0'; --In this line, count4 is initialized as 0.
signal count8 : std_logic_vector (1 downto 0) := "00"; -- Count 8 is initialized as 0.
signal clkdividedby2_temp,clkdividedby4_temp,clkdividedby8_temp : std_logic :='0';
begin
process(clk)
begin
if(rising_edge(clk)) then
clkdividedby2_temp<= not clkdividedby2_temp;
count4 <= count4 + '1';
count8 <= count8 + "01";
if(count4 = '1') then -- = Tests for equality, not ==
clkdividedby4_temp<= not clkdividedby4_temp;
count4<='0';
end if;
if(count8 = "11") then
clkdividedby8_temp<= not clkdividedby8_temp;
count8<="00";
end if;
end if;
end process;
clkdividedby2<=clkdividedby2_temp;
clkdividedby4<=clkdividedby4_temp;
clkdividedby8<=clkdividedby8_temp;
end karakter;
This synthesized perfectly on ISE 10.1 in school, but in Quartus 2, I get the error:
Can't determine definition of operator ""+"" — found 0 possible definitions
I have no idea why this is happening. I wrote all the libraries and stuff, and it is still not working.
Best Answer
You are trying to perform addition on
std_logic
andstd_logic_vector
-- that makes no sense in VHDL, because these types do not hold numerical values.If you want addition to work, you need to use either
'1'
values meet in an addition, orFor a counter that is only compared against a fixed value, but never read, I'd go with the latter, change the type to
natural
and give it arange
constraint, and leave it up to the compiler to select an internal representation.