Electronic – Quartus FPGA migration issues

intel-fpgaquartus-iivhdl

I have an FPGA design Quartus that compiles and works correctly for a cyclone IV EP4CE15F17C8 (42% used).

I'm trying to migrate same design to a smaller FPGA EP4CE10F17C8, but when changing FPGA device I get compilation errors related to a PLL Megafunction I have:

Error (176554): Can't place PLL "top_level_d9620:top_level_d9620_comp|pll25MHZ_b:G5|altpll:altpll_component|pll25MHZ_b_altpll:auto_generated|pll1" — I/O pin clock (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device

I don't know how to avoid this error. Is there a workaround for this? Even if I remove the PLL, I get many errors like this:

Error (176337): Cell top_laser:top_laser_comp|gene_freq_dpi1:U35|retard_t40[0] fed by 5 non-global control signals — only 4 control signals may be non-global

Any ideas?

Best Answer

Looks like you might be using an input pin for the clock that isn't a clock capable pin. Take a look at the datasheet and make sure you're using a valid clock pin. This is one of the few things on an FPGA that you really have to watch out for specifically what pin you're using. Other signals can basically be placed wherever it is most convenient, but clocks must be connected to pins capable of driving the clock networks and PLLs.

Not sure about the second error, though. See: http://quartushelp.altera.com/13.0/mergedProjects/msgs/msgs/efsac_fsac_too_many_non_global_control_signals_for_lcell_ff.htm . Might be a clock routing issue if the clock is not going over the proper clock network.

Related Solutions

Electronic – Specify include path in Quartus II

Altera recommends that you use the SEARCH_PATH assignment to define the project libraries. You can have multiple SEARCH_PATH assignments. However, you can specify only one source directory for each SEARCH_PATH assignment.

For example:

set_global_assignment -name SEARCH_PATH "../other_dir/library1"
set_global_assignment -name SEARCH_PATH "../other_dir/library2"
set_global_assignment -name SEARCH_PATH "../other_dir/library3"

Please refer to Managing Quartus II Projects document for more details.

FPGA Synthesis = 0 LE (Altera Quartus II)

Without the code, you can only expect general advice.

However the most likely scenario is that the outputs don't actually depend on the inputs, so that optimisation eliminates all the logic in between them and hardwires the outputs to '1', '0' or 'Z'.

This can often be due to a mistake in your logic, or a reflection of the fact that you are trying out an incomplete design, and the missing portions contain logic that would prevent the optimisation from deleting what you have done so far.

Best Answer

Related Solutions

Electronic – Specify include path in Quartus II

FPGA Synthesis = 0 LE (Altera Quartus II)

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