Electronic – repairing damage: what size ceramic bypass capacitor

There should be a low ESR cap immediately on the output of each regulator. Perhaps 100 nF as you show is the minimum, but I'd put more there unless it was specifically disallowed in the datasheet. If they're supposed to work with 100 nF, then 1 µF ceramic sounds good.

As for the input, you can't have too much capacitance on the input of a regulator. Put what you can get in 0805 immediately on the input. That should be more than the skimpy values you are trying to squeak by with.

1. Place a decoupling capacitor near every power supply pin of each digital IC, if at all possible.

2. Typically, this should be 0.1 uF or higher ceramic multi-layer chip capacitor (MLCC), in the smallest package your assembler is comfortable working with. For your scenario I'd recommend 0402, but 0603 would also be fine if you are doing hand assembly.

   Choose parts with decent over-temperature and over-voltage stability. Typically this means choosing the "X7R" type.

3. Place higher-value bulk bypassing capacitors around the board, but not necessarily at each power pin.

I've seen references of adding a few capacitors at each IC, differing by "decade capacitance".

I agree with this rule. Spreading the capacitor values by more than a decade increases the risk of running into anti-resonance, which causes very high power supply impedance at certain frequencies. This is explained in a very good Murata app note.

However, I'd like to know if there are other recommendations. How about adding a 1uF or a 0.001uF in parallel as well?

In most scenarios, adding lower-value capacitors in the same size package as your primary decoupling capacitors will be counter-productive, as it will push the primary decoupling capacitors farther away from the power supply pins and increase their effective series inductance.