Electronic – Resources to learn about the AVR/RISC architecture

Looking at an entity, how can one determine the actual architectural model being used without hints from the architecture name?

You can't - when it is instantiated or configured the architecture can be specified (if there is more than one to choose from) or a default will be chosen for you.

If specifying multiple architectures for a single entity (which I understand is possible) do you simply give the architectures different names in the same file or...?

You give them different names. It doesn't have to be within the same file (in fact VHDL cares a lot less than you might think about what's in what file)

Are the architecture names confined to a given entity (that is, is there any problem with "namespaces" by using the same architecture name over multiple entities)?

They are "attached" to an entity, so can be reused.

I often use a1 as my architecture for everything synthesisable as

• rtl implies lower level (to many readers) than I write at.
• behavioural often implies non-synthesisable (to some readers)
• synth is used by the synthesiser for it's model (otherwise I'd have used that)

a1 has been non-conflicted so far and doesn't cause confusion ;)

If I actually have more than one architecture, I tend to name them verbosely (for example hard_multipliers and lut_multipliers for a filter which instantiates - or not - MUL18 blocks).

Very often you only have one architecture, so it doesn't matter. Good entity names are much more important.

It seems there is a distinction between RTL and behavioral, but as mentioned above I'm not really seeing it in the examples I've seen (often I only see one architecture being defined). Is one architecture more common than the others?

It's historical - you didn't used to be able to synthesise "behavioural" code (which at one point included things like adding!) - so you created an RTL version which instantiated adders and the like. (That's as I understand it - I've been writing behavioural (and yet still synthesisable) code since I started VHDLing in about 1999!)

No answers; here's what I discovered:

• Of these three, only the JTAGICE-mkII is supported by AVR Studio 4. It's also old, expensive, and (relatively) slow.
• The JTAGICE3 is the de-facto standard for a lesser-expensive Atmel JTAG programmer/debugger, and is supported in AS5 and AS6.
• The ATMEL-ICE is brand new, represents Atmel's attempt to hit the lower-cost market, and is supposedly better than the JTAGICE3 in every way (speed, breakpoints, etc). However, it hasn't gone through it's "new product growing pains" yet...

I chose to get the JTAGICE3, and migrate to Atmel Studio 6. The migration was easy. It took a while to figure out how to make the debugging work with AS6, but now it's working fine.