Electronic – Setting Pin Assignments For Quartus

fpgaintel-fpgapinsquartus

So I have written a simple Verilog module which works well in the ModelSim emulator. I would like to now program my Cyclone 10 Dev board to perform this simple task, but I need to set up the pin assignments on my qsf file.

That being said, I don't know where to find the correct pins and how I would assign them to the inputs and outputs of my module. The model I am using is a 10CL025YU256I7G

Best Answer

I believe you're using the Intel® Cyclone® 10 LP FPGA Evaluation Kit.

Here's the user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-lp-eval-kit.pdf

In that document it lists the the user i/o LEDs, push-buttons, switches, and others which you may want to use:

From the schematic you can see the names of the pins those are attached to those i/o in black.

https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/cyclone10/c10lp-eval-a1-sch.PDF

You can then assign them to your module's nets with settings such the following in your QSF:

set_location_assignment PIN_M16 -to your_hdl_signal

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FPGA outputs are always high with basic and/or program

Since this is your first FPGA project with this board, there are several things that could be going wrong. (I go through this kind of thing myself with every new development system)

Maybe the board isn't powered -- the Amazon link doesn't say whether this board includes the required 5V DC power supply. If this is anything like the ones on ebay, the board should come already loaded with some code that lights up the LEDs. Normally an FPGA board vendor loads a test program onto the board to prove there are no assembly errors, before they ship the board. So when it is first powered up, I'd expect to see an LED light up.

Maybe the JTAG programmer was connected to the wrong header -- this board has two different 2x5 shrouded headers, one for JTAG loading and the other for SPI platform flash loading.

Maybe the design is actually working? How are you testing it? I know that EP2C5T144 board doesn't have much on/board switches and LEDs. The input and output pins are on dual-row headers. It's easy to mis-count or get the inner row / outer row connection swapped. I looked through your project report files and don't see anything wrong. To test this code, you'd have to connect some wires to your in_1, in_2, in_3 and connect each to either 3.3V or GND. Then go through the "truth table" combinations, and observe the output.

Your example HDL code was correctly translated, based on this part of the log file:

Info (21057): Implemented 7 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 3 input pins
    Info (21059): Implemented 2 output pins
    Info (21061): Implemented 2 logic cells

This is exactly the resource usage I'd expect for a pair of three-input gates. I also checked through the other reports to see if any of the logic got removed by later stages, but it looks to me like it got through place/route/map and should have ended up in the final configuration bitstream.

On a side note: it's good practice to use net names like "in_1", "out_1" like you used in logic.v, instead of just "1" - "5". Makes it easier to understand what's intended. The pinout report (BasicLogic.pin) would be easier to read if the toplevel net names matched up with your HDL code.

Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
-------------------------------------------------------------------------------------------------------------
1                            : 40        : input  : 3.3-V LVTTL       :         : 4         : Y              
2                            : 41        : input  : 3.3-V LVTTL       :         : 4         : Y              
3                            : 42        : input  : 3.3-V LVTTL       :         : 4         : Y              
4                            : 71        : output : 3.3-V LVTTL       :         : 4         : Y              
5                            : 72        : output : 3.3-V LVTTL       :         : 4         : Y

Suggestion: try an LED blinker project next. Just use a 24-bit counter (clocked by the on-board 50MHz system clock) and the MSB of that counter should blink slow enough you can see it blink, but fast enough you know it's doing something. I've learned the hard way to always include an LED blinker diagnostic on my projects, so I can confirm that the FPGA actually got programmed with valid code.

Electronic – Why does this Verilog code produce no output on the FPGA

You do not drive LEDR output at all. You need an assignment like:

assign LEDR = M;

You probably wanted to achieve that by assigning LEDR[3:0] to M (i.e. assign M = LEDR[3:0]), but this two assignments are not equivalent in Verilog.

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FPGA outputs are always high with basic and/or program

Electronic – Why does this Verilog code produce no output on the FPGA

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