finfetmosfetvlsi
I read that FinFET transistors were introduced to avoid the problems due to downscaling of MOSFET size, ie reduce the Short Channel Effects (SCEs) like DIBL, Hot Electron effects etc.
But how does the FinFET overcome these problems?
Or am I wrong? Is FinFET released to overcome any other problems in present planar MOSFETs?
When using high-side N-channel MOSFETs, a MOSFET driver chip is generally used (e.g., an IR2130). These chips require a boost capacitor which allows the gates of the high-side MOSFETs to be driven with the required voltage. The downside of this is that the MOSFET driver has a restricted operating range (typically 10V-20V). The second down-side is that you can't drive the MOSFETS to 100% pulse-width; this is usually not a problem. Alternatively you could use P-channel high-side MOSFETs and N-channel for the low-side. With this configuration, you can PWM the low-side switches only and save some power. (You can do this with all N-channels as well, it's just trickier since you have to keep the boost capacitors charged). Go to Digikey and search for "mosfet driver", you'll want the 3-phase bridge drivers specified for external switches.
As for the MOSFETs themselves, I don't recommend you use them in parallel. This would increase your footprint as well as your gate charge. Instead, look for high-current mosfets on Digikey. My favorite packages for these are D-Pak, 8-PowerVDFN, and PowerPAK 1212-8.
Atmel has an app note for sensor-based and sensor-less motor control. Unfortunately AVRs don't have much processing power and your control algorithm will likely be restricted to fixed-point math because of this. Because of the processing power limitations, you may want to consider not using the Arduino environment and instead use straight C or assembly.
You may have some trouble isolating the I2C bus optically since it's a bi-directional bus. If you were to use a communication system with single direction lines, you may want to look at TI's line of isolator chips (e.g., the ISO7221).
To turn on any of the MOSFETs properly in your circuit, the gate voltage has to be significantly higher than the source voltage. For the lower position devices Q2 and Q4, the sources are grounded to 0V therefore they can easily turn on into "saturation" by applying a gate voltage of a few volts above ground.
For the devices connected to the top rail, if you want the on-resistance between drain and source to be really low you have to obey the same rule - the drive voltage to the gate has to be several volts above the source. Now for low volt drop you want the source to be switched virtually to 6V - where in the circuit can the gate receive a voltage of maybe 9 or 10 volts?
There isn't one so please consider two options: -
Now the relays. What are you hoping to achieve here? The MOSFET whose gate is disconnected will float to some almost random voltage level and possibly turn on unexpectedly or just get hot. Get rid of the relays unless you have some cunning plan for their use which eludes me.
This is a standard H bridge using P and N MOSFETs: -
Please ask if you need recommendations for devices.
Best Answer
finFETs are new generation transistors which utilize tri-gate structure. In contrast to planar transistors where the Gate electrode was (usually) above the channel, the Gate electrode "wraps" the channel from three sides in finFETs:
The immediate and obvious advantage of finFETs is that the effective width of the channel becomes:
$$W_{eff}=2H_{Si}+W_{Si}$$
The above dependence is revolutionary in that the current capability of the transistor (which is lineaw in \$W_{eff}\$) may be increased by employing the "vertical dimension" - the transistor's height affects its current capability. However, it is not that simple to increase the height of the fins - there are many physical issues which must be addressed.
There are basically two major technologies for finFETs manufacturing: Silicon-on-Insulator (SOI) finFETs and Bulk finFETs:
The very first finFETs were manufactured on top of insulating layer. The fact that the current can't flow "underneath" the gate when the transistor is in OFF state reduces the leakage current. Alternative techniques for stopping leakage current from flowing in the bulk were introduced later, which allowed for manufacturing of Bulk finFETs. This technique utilizes very high doping gradients along the height of the fin in order to prevent the current from flowing in the bulk.
It is true that finFETs allow for reducing of DIBL effect due to intrinsically higher level of Gate control over the channel. This control comes from the fact that may depletion regions are bounded by the fin itself and do not extend into the bulk. However DIBL is still one of the major factors which affects finFETs threshold voltages. The following graph shows the profiles of constant DIBL on height ratio vs. width ratio graph:
One of the advantages of Bulk finFETs is apparent from the above graph: constrained by the same DIBL level, higher doping Bulk finFETs allow for physically higher fins (higher \$W_{eff}\$) as compared to SOI ones.
The fact that there is tight connection between \$W_{eff}\$ and \$L_D\$ is not special for finFETs - all deep submicron planar technologies also suffer from narrow width effects.
This was the basic overview of finFETs. I'm not that into their physics for more elaborate explanations.
As for finFETs adoption: Intel has already adopted finFETs (if I'm not mistaken, starting with 22nm technology). TSMC and Global Foundries are going to introduce their finFET processes in a few months (or, maybe, they have already introduced them).