Electronic – Should all Combinations be included in a truth table

Your circuit needs to be started in a known state, and if the default is to be with the 4013's Q low and both 4017s' Q0s high, then to that end I've taken the liberty of redrawing your circuit, below, to include the Power-On-Reset using diodes to make it compatible with the rest of your diode logic.

Note that your R5 isn't needed since the diodes are being driven by a CMOS totem pole which never floats.

Just for fun I've also added in some arbitrary clocks - to make it run - and, below, included a version of your circuit - with the same functionality but simplified by eliminating all the diodes and their associated resistors and replacing them with CD4071 OR gates. The LTspice files needed to play with the circuits or run simulations, if you want to, are here

I believe you are missing some basic concepts about sequential circuits. First of all, while combinational circuits are stateless, sequential circuits are defined by the fact of having some kind of inner state that can be changed either in precise instants of time (synchronous circuits) or when a certain condition is true (asynchronous circuits).

The cool thing about synchronous sequential circuits is that they can be realized by combining only two different ingredients:

• combinational logic, which might be the 2-level logic that can be realized with Karnaugh maps or more complex multi-level logic;
• flip flops, similar to the one you asked about (though most of the time you use a single-edge-triggered flip flop).

So basically to design a generic synchronous circuit you divide it in a combinational part and in registers (flip flops). To do this you must have a model of what you're doing; an example of a simple and useful one is that of Moore finite state machines in which you have a state \$S\$, an input \$x\$ and an output \$y\$. A combinational circuit \$C_s\$ is used to compute the new state as \$S'=f_{C_s}(S, x)\$, a second combinational circuit \$C_y\$ is used to compute the new output from the current state as \$y=g_{C_y}(S)\$ and the state is memorized in flip flops. Many other models exists apart from this one (e.g. Mealy finite state machines) but the constant is that your problem is always decomposed in a designing/synthesizing a set of combinational circuits and using flip flops. This can be done very efficiently by automatic synthesis tools from an RTL input such as Verilog, SystemVerilog or VHDL code.

But one problem remains: how to design flip flops then? Flip-flops themselves are neither synchronous circuits nor combinational circuits. They are the most famous representative of the category of asynchronous circuits. The most famous type of flip flop, the master-slave edge triggered one, is a relatively complex circuit composed by a sequence of two set-reset latches that are transparent on opposite phases of the clock. Each latch is composed by two simple gates in a feedback chain (see Wikipedia for details). In any case, the flip flop has to be designed very carefully so that it behaves as the ideal edge-triggered flip flop, sampling the input exactly at the clock edge (real flip flops have a setup time constraint, during which the input datum must be stable before sampling, and a hold time one during which the datum must be kept stable after sampling).

Unfortunately, there are no simple general methods for designing asynchronous circuits; in fact, such methods are a somewhat active field of research in the electronic design automation community.